diff --git a/cranelift/filetests/regalloc/aliases.cton b/cranelift/filetests/regalloc/aliases.cton new file mode 100644 index 0000000000..575fedd923 --- /dev/null +++ b/cranelift/filetests/regalloc/aliases.cton @@ -0,0 +1,36 @@ +test compile +set is_64bit +isa intel haswell + +function %value_aliases(i32, f32, i64 vmctx) spiderwasm { + gv0 = vmctx + heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 + +ebb0(v0: i32, v1: f32, v2: i64): + v3 = iconst.i32 0 + jump ebb3(v3) + +ebb3(v4: i32): + v5 = heap_addr.i64 heap0, v4, 1 + v6 = load.f32 v5 + v7 -> v1 + v8 = fdiv v6, v7 + v9 = heap_addr.i64 heap0, v4, 1 + store v8, v9 + v10 = iconst.i32 4 + v11 = iadd v4, v10 + v12 -> v0 + v13 = icmp ult v11, v12 + v14 = bint.i32 v13 + brnz v14, ebb3(v11) + jump ebb4 + +ebb4: + jump ebb2 + +ebb2: + jump ebb1 + +ebb1: + return +} diff --git a/lib/cretonne/src/regalloc/liveness.rs b/lib/cretonne/src/regalloc/liveness.rs index 8faa8131c6..5dd6ce71bb 100644 --- a/lib/cretonne/src/regalloc/liveness.rs +++ b/lib/cretonne/src/regalloc/liveness.rs @@ -366,7 +366,7 @@ impl Liveness { /// Compute the live ranges of all SSA values used in `func`. /// This clears out any existing analysis stored in this data structure. - pub fn compute(&mut self, isa: &TargetIsa, func: &Function, cfg: &ControlFlowGraph) { + pub fn compute(&mut self, isa: &TargetIsa, func: &mut Function, cfg: &ControlFlowGraph) { self.ranges.clear(); // Get ISA data structures used for computing live range affinities. @@ -386,6 +386,9 @@ impl Liveness { } for inst in func.layout.ebb_insts(ebb) { + // Eliminate all value aliases, they would confuse the register allocator. + func.dfg.resolve_aliases_in_arguments(inst); + // Make sure we have created live ranges for dead defs. // TODO: When we implement DCE, we can use the absence of a live range to indicate // an unused value.