diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 71500f7c7d..e7549a0841 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -1619,7 +1619,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                 let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
                 ctx.emit(Inst::gen_move(dst, src, ty));
                 let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-                ctx.emit(Inst::equals(ty, RegMem::from(tmp), tmp));
+
+                // Set tmp to all 1s before flipping the bits
+                ctx.emit(Inst::equals(types::I32X4, RegMem::from(tmp), tmp));
                 ctx.emit(Inst::xor(ty, RegMem::from(tmp), dst));
             } else if ty == types::I128 || ty == types::B128 {
                 let src = put_input_in_regs(ctx, inputs[0]);
diff --git a/tests/misc_testsuite/simd/issue_3327_bnot_lowering.wast b/tests/misc_testsuite/simd/issue_3327_bnot_lowering.wast
new file mode 100644
index 0000000000..0d30c630d7
--- /dev/null
+++ b/tests/misc_testsuite/simd/issue_3327_bnot_lowering.wast
@@ -0,0 +1,10 @@
+(; See issue https://github.com/bytecodealliance/wasmtime/issues/3327 ;)
+
+(module
+  (func $v128_not (export "v128_not") (result v128)
+    v128.const f32x4 0 0 0 0
+    f32x4.abs
+    v128.not)
+)
+
+(assert_return (invoke "v128_not") (v128.const i32x4 -1 -1 -1 -1))
\ No newline at end of file