diff --git a/cranelift/filetests/isa/x86/prologue-epilogue.cton b/cranelift/filetests/isa/x86/prologue-epilogue.cton
index 41d2147438..249f2a9ff9 100644
--- a/cranelift/filetests/isa/x86/prologue-epilogue.cton
+++ b/cranelift/filetests/isa/x86/prologue-epilogue.cton
@@ -228,4 +228,4 @@ ebb4:
 
 ; check: function %divert
 ; check: regmove v5, %rcx -> %rbx
-; check: [RexOp1popq#58,%rbx]                v15 = x86_pop.i64
+; check: [Op1popq#58,%rbx]                   v15 = x86_pop.i64
diff --git a/lib/codegen/meta/isa/x86/encodings.py b/lib/codegen/meta/isa/x86/encodings.py
index 65c28b1191..2284a0d70f 100644
--- a/lib/codegen/meta/isa/x86/encodings.py
+++ b/lib/codegen/meta/isa/x86/encodings.py
@@ -126,7 +126,13 @@ enc_i32_i64(x86.umulx, r.mulx, 0xf7, rrr=4)
 
 enc_i32_i64(base.copy, r.umr, 0x89)
 enc_both(base.copy.b1, r.umr, 0x89)
-enc_i32_i64(base.regmove, r.rmov, 0x89)
+
+# For x86-64, only define REX forms for now, since we can't describe the
+# special regunit immediate operands with the current constraint language.
+X86_32.enc(base.regmove.i32, *r.rmov(0x89))
+X86_64.enc(base.regmove.i32, *r.rmov.rex(0x89))
+X86_64.enc(base.regmove.i64, *r.rmov.rex(0x89, w=1))
+
 enc_both(base.regmove.b1, r.rmov, 0x89)
 enc_both(base.regmove.i8, r.rmov, 0x89)
 
@@ -251,6 +257,8 @@ X86_32.enc(x86.pop.i32, *r.popq(0x58))
 enc_x86_64(x86.pop.i64, r.popq, 0x58)
 
 # Copy Special
+# For x86-64, only define REX forms for now, since we can't describe the
+# special regunit immediate operands with the current constraint language.
 X86_64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
 X86_32.enc(base.copy_special, *r.copysp(0x89))
 
@@ -528,8 +536,16 @@ X86_64.enc(base.bitcast.i64.f64, *r.rfumr.rex(0x66, 0x0f, 0x7e, w=1))
 # movaps
 enc_both(base.copy.f32, r.furm, 0x0f, 0x28)
 enc_both(base.copy.f64, r.furm, 0x0f, 0x28)
-enc_both(base.regmove.f32, r.frmov, 0x0f, 0x28)
-enc_both(base.regmove.f64, r.frmov, 0x0f, 0x28)
+
+# For x86-64, only define REX forms for now, since we can't describe the
+# special regunit immediate operands with the current constraint language.
+X86_32.enc(base.regmove.f32, *r.frmov(0x0f, 0x28))
+X86_64.enc(base.regmove.f32, *r.frmov.rex(0x0f, 0x28))
+
+# For x86-64, only define REX forms for now, since we can't describe the
+# special regunit immediate operands with the current constraint language.
+X86_32.enc(base.regmove.f64, *r.frmov(0x0f, 0x28))
+X86_64.enc(base.regmove.f64, *r.frmov.rex(0x0f, 0x28))
 
 # cvtsi2ss
 enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)
diff --git a/lib/codegen/src/context.rs b/lib/codegen/src/context.rs
index 986ae74d85..c2aab76bad 100644
--- a/lib/codegen/src/context.rs
+++ b/lib/codegen/src/context.rs
@@ -141,12 +141,9 @@ impl Context {
         }
         self.regalloc(isa)?;
         self.prologue_epilogue(isa)?;
-        // Temporarily disable the shrink_instructions pass, as it causes miscompiles.
-        /*
         if isa.flags().opt_level() == OptLevel::Best {
             self.shrink_instructions(isa)?;
         }
-        */
         self.relax_branches(isa)
     }