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[AArch64] Merge 32- and 64-bit BitOps (#3840)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-02-23 19:36:23 +00:00
committed by GitHub
parent d307a4ab9a
commit 5b7df72bce
7 changed files with 541 additions and 610 deletions
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13
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -879,14 +879,15 @@ impl MachInstEmit for Inst {
sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
}
&Inst::BitRR { op, rd, rn, .. } => {
let size = if op.operand_size().is32() { 0b0 } else { 0b1 };
&Inst::BitRR {
op, size, rd, rn, ..
} => {
let (op1, op2) = match op {
BitOp::RBit32 | BitOp::RBit64 => (0b00000, 0b000000),
BitOp::Clz32 | BitOp::Clz64 => (0b00000, 0b000100),
BitOp::Cls32 | BitOp::Cls64 => (0b00000, 0b000101),
BitOp::RBit => (0b00000, 0b000000),
BitOp::Clz => (0b00000, 0b000100),
BitOp::Cls => (0b00000, 0b000101),
};
sink.put4(enc_bit_rr(size, op1, op2, rn, rd))
sink.put4(enc_bit_rr(size.sf_bit(), op1, op2, rn, rd))
}
&Inst::ULoad8 { rd, ref mem, flags }

18
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -1262,7 +1262,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::RBit32,
op: BitOp::RBit,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(10),
},
@@ -1272,7 +1273,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::RBit64,
op: BitOp::RBit,
size: OperandSize::Size64,
rd: writable_xreg(1),
rn: xreg(10),
},
@@ -1282,7 +1284,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::Clz32,
op: BitOp::Clz,
size: OperandSize::Size32,
rd: writable_xreg(15),
rn: xreg(3),
},
@@ -1292,7 +1295,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::Clz64,
op: BitOp::Clz,
size: OperandSize::Size64,
rd: writable_xreg(15),
rn: xreg(3),
},
@@ -1302,7 +1306,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::Cls32,
op: BitOp::Cls,
size: OperandSize::Size32,
rd: writable_xreg(21),
rn: xreg(16),
},
@@ -1312,7 +1317,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::BitRR {
op: BitOp::Cls64,
op: BitOp::Cls,
size: OperandSize::Size64,
rd: writable_xreg(21),
rn: xreg(16),
},

32
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -58,35 +58,12 @@ pub enum FPUOpRI {
}
impl BitOp {
/// What is the opcode's native width?
pub fn operand_size(&self) -> OperandSize {
match self {
BitOp::RBit32 | BitOp::Clz32 | BitOp::Cls32 => OperandSize::Size32,
_ => OperandSize::Size64,
}
}
/// Get the assembly mnemonic for this opcode.
pub fn op_str(&self) -> &'static str {
match self {
BitOp::RBit32 | BitOp::RBit64 => "rbit",
BitOp::Clz32 | BitOp::Clz64 => "clz",
BitOp::Cls32 | BitOp::Cls64 => "cls",
}
}
}
impl From<(Opcode, Type)> for BitOp {
/// Get the BitOp from the IR opcode.
fn from(op_ty: (Opcode, Type)) -> BitOp {
match op_ty {
(Opcode::Bitrev, I32) => BitOp::RBit32,
(Opcode::Bitrev, I64) => BitOp::RBit64,
(Opcode::Clz, I32) => BitOp::Clz32,
(Opcode::Clz, I64) => BitOp::Clz64,
(Opcode::Cls, I32) => BitOp::Cls32,
(Opcode::Cls, I64) => BitOp::Cls64,
_ => unreachable!("Called with non-bit op!: {:?}", op_ty),
BitOp::RBit => "rbit",
BitOp::Clz => "clz",
BitOp::Cls => "cls",
}
}
}
@@ -2239,8 +2216,7 @@ impl Inst {
let extendop = extendop.show_rru(mb_rru);
format!("{} {}, {}, {}, {}", op, rd, rn, rm, extendop)
}
&Inst::BitRR { op, rd, rn } => {
let size = op.operand_size();
&Inst::BitRR { op, size, rd, rn } => {
let op = op.op_str();
let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
let rn = show_ireg_sized(rn, mb_rru, size);