x64: Take SIGFPE signals for divide traps (#6026)

* x64: Take SIGFPE signals for divide traps

Prior to this commit Wasmtime would configure `avoid_div_traps=true`
unconditionally for Cranelift. This, for the division-based
instructions, would change emitted code to explicitly trap on trap
conditions instead of letting the `div` x86 instruction trap.

There's no specific reason for Wasmtime, however, to specifically avoid
traps in the `div` instruction. This means that the extra generated
branches on x86 aren't necessary since the `div` and `idiv` instructions
already trap for similar conditions as wasm requires.

This commit instead disables the `avoid_div_traps` setting for
Wasmtime's usage of Cranelift. Subsequently the codegen rules were
updated slightly:

* When `avoid_div_traps=true`, traps are no longer emitted for `div`
  instructions.
* The `udiv`/`urem` instructions now list their trap as divide-by-zero
  instead of integer overflow.
* The lowering for `sdiv` was updated to still explicitly check for zero
  but the integer overflow case is deferred to the instruction itself.
* The lowering of `srem` no longer checks for zero and the listed trap
  for the `div` instruction is a divide-by-zero.

This means that the codegen for `udiv` and `urem` no longer have any
branches. The codegen for `sdiv` removes one branch but keeps the
zero-check to differentiate the two kinds of traps. The codegen for
`srem` removes one branch but keeps the -1 check since the semantics of
`srem` mismatch with the semantics of `idiv` with a -1 divisor
(specifically for INT_MIN).

This is unlikely to have really all that much of a speedup but was
something I noticed during #6008 which seemed like it'd be good to clean
up. Plus Wasmtime's signal handling was already set up to catch
`SIGFPE`, it was just never firing.

* Remove the `avoid_div_traps` cranelift setting

With no known users currently removing this should be possible and helps
simplify the x64 backend.

* x64: GC more support for avoid_div_traps

Remove the `validate_sdiv_divisor*` pseudo-instructions and clean up
some of the ISLE rules now that `div` is allowed to itself trap
unconditionally.

* x64: Store div trap code in instruction itself

* Keep divisors in registers, not in memory

Don't accidentally fold multiple traps together

* Handle EXC_ARITHMETIC on macos

* Update emit tests

* Update winch and tests

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -73,8 +73,6 @@ impl Inst {
             | Inst::CallUnknown { .. }
             | Inst::CheckedSRemSeq { .. }
             | Inst::CheckedSRemSeq8 { .. }
-            | Inst::ValidateSdivDivisor { .. }
-            | Inst::ValidateSdivDivisor64 { .. }
             | Inst::Cmove { .. }
             | Inst::CmpRmiR { .. }
             | Inst::CvtFloatToSintSeq { .. }
@@ -225,6 +223,7 @@ impl Inst {
     pub(crate) fn div(
         size: OperandSize,
         sign: DivSignedness,
+        trap: TrapCode,
         divisor: RegMem,
         dividend_lo: Gpr,
         dividend_hi: Gpr,
@@ -235,6 +234,7 @@ impl Inst {
         Inst::Div {
             size,
             sign,
+            trap,
             divisor: GprMem::new(divisor).unwrap(),
             dividend_lo,
             dividend_hi,
@@ -245,6 +245,7 @@ impl Inst {
 
     pub(crate) fn div8(
         sign: DivSignedness,
+        trap: TrapCode,
         divisor: RegMem,
         dividend: Gpr,
         dst: WritableGpr,
@@ -252,6 +253,7 @@ impl Inst {
         divisor.assert_regclass_is(RegClass::Int);
         Inst::Div8 {
             sign,
+            trap,
             divisor: GprMem::new(divisor).unwrap(),
             dividend,
             dst,
@@ -548,10 +550,6 @@ impl Inst {
         Inst::JmpUnknown { target }
     }
 
-    pub(crate) fn trap_if(cc: CC, trap_code: TrapCode) -> Inst {
-        Inst::TrapIf { cc, trap_code }
-    }
-
     /// Choose which instruction to use for loading a register value from memory. For loads smaller
     /// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
     /// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
@@ -771,6 +769,7 @@ impl PrettyPrint for Inst {
             Inst::Div {
                 size,
                 sign,
+                trap,
                 divisor,
                 dividend_lo,
                 dividend_hi,
@@ -785,7 +784,7 @@ impl PrettyPrint for Inst {
                 let dst_remainder =
                     pretty_print_reg(dst_remainder.to_reg().to_reg(), size.to_bytes(), allocs);
                 format!(
-                    "{} {}, {}, {}, {}, {}",
+                    "{} {}, {}, {}, {}, {} ; trap={trap}",
                     ljustify(match sign {
                         DivSignedness::Signed => "idiv".to_string(),
                         DivSignedness::Unsigned => "div".to_string(),
@@ -800,6 +799,7 @@ impl PrettyPrint for Inst {
 
             Inst::Div8 {
                 sign,
+                trap,
                 divisor,
                 dividend,
                 dst,
@@ -808,7 +808,7 @@ impl PrettyPrint for Inst {
                 let dividend = pretty_print_reg(dividend.to_reg(), 1, allocs);
                 let dst = pretty_print_reg(dst.to_reg().to_reg(), 1, allocs);
                 format!(
-                    "{} {dividend}, {divisor}, {dst}",
+                    "{} {dividend}, {divisor}, {dst} ; trap={trap}",
                     ljustify(match sign {
                         DivSignedness::Signed => "idiv".to_string(),
                         DivSignedness::Unsigned => "div".to_string(),
@@ -874,27 +874,6 @@ impl PrettyPrint for Inst {
                 format!("checked_srem_seq {dividend}, {divisor}, {dst}")
             }
 
-            Inst::ValidateSdivDivisor {
-                dividend,
-                divisor,
-                size,
-            } => {
-                let dividend = pretty_print_reg(dividend.to_reg(), size.to_bytes(), allocs);
-                let divisor = pretty_print_reg(divisor.to_reg(), size.to_bytes(), allocs);
-                format!("validate_sdiv_divisor {dividend}, {divisor}")
-            }
-
-            Inst::ValidateSdivDivisor64 {
-                dividend,
-                divisor,
-                tmp,
-            } => {
-                let dividend = pretty_print_reg(dividend.to_reg(), 8, allocs);
-                let divisor = pretty_print_reg(divisor.to_reg(), 8, allocs);
-                let tmp = pretty_print_reg(tmp.to_reg().to_reg(), 8, allocs);
-                format!("validate_sdiv_divisor {dividend}, {divisor} {tmp}")
-            }
-
             Inst::SignExtendData { size, src, dst } => {
                 let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
                 let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
@@ -1917,21 +1896,6 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
             collector.reg_fixed_def(dst_hi.to_writable_reg(), regs::rdx());
             src2.get_operands(collector);
         }
-        Inst::ValidateSdivDivisor {
-            dividend, divisor, ..
-        } => {
-            collector.reg_use(divisor.to_reg());
-            collector.reg_use(dividend.to_reg());
-        }
-        Inst::ValidateSdivDivisor64 {
-            dividend,
-            divisor,
-            tmp,
-        } => {
-            collector.reg_use(divisor.to_reg());
-            collector.reg_use(dividend.to_reg());
-            collector.reg_early_def(tmp.to_writable_reg());
-        }
         Inst::SignExtendData { size, src, dst } => {
             match size {
                 OperandSize::Size8 => {