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Verify that type variables have been fully bound.

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The shift instructions have two type variables since the shift amount can be a
differently sized integer. Fix the RISC-V shift encodings to reflect this, and
allow i64 registers to be shifted by an i32 amount.
This commit is contained in:
Jakob Stoklund Olesen
2016-08-04 10:21:48 -07:00
parent a1cc8af186
commit 5a8293427d
2 changed files with 40 additions and 11 deletions
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14
meta/target/riscv/encodings.py
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@@ -10,12 +10,20 @@ from recipes import OP, R
for inst, f3, f7 in [
(base.iadd, 0b000, 0b0000000),
(base.isub, 0b000, 0b0100000),
(base.ishl, 0b001, 0b0000000),
(base.ushr, 0b101, 0b0000000),
(base.sshr, 0b101, 0b0100000),
(base.bxor, 0b100, 0b0000000),
(base.bor, 0b110, 0b0000000),
(base.band, 0b111, 0b0000000)
]:
RV32.enc(inst.i32, R, OP(f3, f7))
RV64.enc(inst.i64, R, OP(f3, f7))
# Dynamic shifts have the same masking semantics as the cton base instructions
for inst, f3, f7 in [
(base.ishl, 0b001, 0b0000000),
(base.ushr, 0b101, 0b0000000),
(base.sshr, 0b101, 0b0100000),
]:
RV32.enc(inst.i32.i32, R, OP(f3, f7))
RV64.enc(inst.i64.i64, R, OP(f3, f7))
# Allow i32 shift amounts in 64-bit shifts.
RV64.enc(inst.i64.i32, R, OP(f3, f7))