CL/aarch64: implement the wasm SIMD i32x4.dot_i16x8_s instruction

This patch implements, for aarch64, the following wasm SIMD extensions

  i32x4.dot_i16x8_s instruction
  https://github.com/WebAssembly/simd/pull/127

It also updates dependencies as follows, in order that the new instruction can
be parsed, decoded, etc:

  wat          to  1.0.27
  wast         to  26.0.1
  wasmparser   to  0.65.0
  wasmprinter  to  0.2.12

The changes are straightforward:

* new CLIF instruction `widening_pairwise_dot_product_s`

* translation from wasm into `widening_pairwise_dot_product_s`

* new AArch64 instructions `smull`, `smull2` (part of the `VecRRR` group)

* translation from `widening_pairwise_dot_product_s` to `smull ; smull2 ; addv`

There is no testcase in this commit, because that is a separate repo.  The
implementation has been tested, nevertheless.

cranelift/codegen/src/isa/aarch64/inst/args.rs

@@ -677,6 +677,9 @@ impl VectorSize {
         }
     }
 
+    /// Produces a `VectorSize` with lanes twice as wide.  Note that if the resulting
+    /// size would exceed 128 bits, then the number of lanes is also halved, so as to
+    /// ensure that the result size is at most 128 bits.
     pub fn widen(&self) -> VectorSize {
         match self {
             VectorSize::Size8x8 => VectorSize::Size16x8,
@@ -689,6 +692,7 @@ impl VectorSize {
         }
     }
 
+    /// Produces a `VectorSize` that has the same lane width, but half as many lanes.
     pub fn halve(&self) -> VectorSize {
         match self {
             VectorSize::Size8x16 => VectorSize::Size8x8,