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Remove the old riscv backend

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This commit is contained in:
bjorn3
2021-06-18 19:25:11 +02:00
parent 9e34df33b9
commit 59e18b7d1b
33 changed files with 33 additions and 2378 deletions
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22
cranelift/src/disasm.rs
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@@ -111,28 +111,6 @@ cfg_if! {
fn get_disassembler(isa: &dyn TargetIsa) -> Result<Capstone> {
let cs = match isa.triple().architecture {
Architecture::Riscv32(_) => {
let mut cs = Capstone::new()
.riscv()
.mode(arch::riscv::ArchMode::RiscV32)
.extra_mode(std::iter::once(arch::riscv::ArchExtraMode::RiscVC))
.build()
.map_err(map_caperr)?;
// See the comment of AArch64 below
cs.set_skipdata(true).map_err(map_caperr)?;
cs
}
Architecture::Riscv64(_) => {
let mut cs = Capstone::new()
.riscv()
.mode(arch::riscv::ArchMode::RiscV64)
.extra_mode(std::iter::once(arch::riscv::ArchExtraMode::RiscVC))
.build()
.map_err(map_caperr)?;
// See the comment of AArch64 below
cs.set_skipdata(true).map_err(map_caperr)?;
cs
}
Architecture::X86_32(_) => Capstone::new()
.x86()
.mode(arch::x86::ArchMode::Mode32)