Remove the old riscv backend

2021-06-18 19:25:11 +02:00
parent 9e34df33b9
commit 59e18b7d1b
33 changed files with 33 additions and 2378 deletions
--- a/cranelift/codegen/Cargo.toml
+++ b/cranelift/codegen/Cargo.toml
@@ -63,7 +63,6 @@ unwind = ["gimli"]
 # If no ISA targets are explicitly enabled, the ISA target for the host machine is enabled.
 x86 = []
 arm64 = []
-riscv = []
 s390x = []
 arm32 = [] # Work-in-progress codegen backend for ARM.

@@ -75,7 +74,6 @@ experimental_x64 = []
 all-arch = [
    "x86",
    "arm64",
-    "riscv",
    "s390x"
 ]