cranelift: Port ineg scalar lowering to ISLE on x64

2022-01-13 15:08:01 -08:00
parent b78731839b
commit 5917f1d2c2
5 changed files with 296 additions and 255 deletions
--- a/cranelift/codegen/src/isa/x64/lower.isle
+++ b/cranelift/codegen/src/isa/x64/lower.isle
@@ -905,6 +905,11 @@
        (or_i128 (shr_i128 src_ amt_)
                 (shl_i128 src_ (sub $I64 (imm $I64 128) (RegMemImm.Reg amt_))))))

+;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type (fits_in_64 ty) (ineg x)))
+      (value_reg (neg ty (put_in_reg x))))
+
 ;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

 (rule (lower (has_type (multi_lane 8 16)