Add an AllocatableSet for registers.

This set of available register units also manages register aliasing in
an efficient way.

Detect if the units in a register straddles mask words. The algorithm
for allocating multi-unit registers expect the whole register to be
inside a single mask word. We could handle this if necessary, but so far
no ISAs need it.

lib/cretonne/meta/cdsl/registers.py

@@ -153,7 +153,12 @@ class RegClass(object):
         start = self.bank.first_unit + self.start
         for a in range(self.count):
             u = start + a * self.width
-            mask[u // 32] |= 1 << (u % 32)
+            b = u % 32
+            # We need fancier masking code if a register can straddle mask
+            # words. This will only happen with widths that are not powers of
+            # two.
+            assert b + self.width <= 32, 'Register straddles words'
+            mask[u // 32] |= 1 << b
 
         return mask