diff --git a/lib/cretonne/meta/isa/__init__.py b/lib/cretonne/meta/isa/__init__.py
index 1bef425c58..33b787f494 100644
--- a/lib/cretonne/meta/isa/__init__.py
+++ b/lib/cretonne/meta/isa/__init__.py
@@ -16,4 +16,4 @@ def all_isas():
     Get a list of all the supported target ISAs. Each target ISA is represented
     as a :py:class:`cretonne.TargetISA` instance.
     """
-    return [riscv.isa]
+    return [riscv.ISA]
diff --git a/lib/cretonne/meta/isa/riscv/__init__.py b/lib/cretonne/meta/isa/riscv/__init__.py
index e187a95c0e..3d5d19ed99 100644
--- a/lib/cretonne/meta/isa/riscv/__init__.py
+++ b/lib/cretonne/meta/isa/riscv/__init__.py
@@ -29,4 +29,4 @@ from . import defs
 from . import encodings, settings # noqa
 
 # Re-export the primary target ISA definition.
-isa = defs.isa.finish()
+ISA = defs.ISA.finish()
diff --git a/lib/cretonne/meta/isa/riscv/defs.py b/lib/cretonne/meta/isa/riscv/defs.py
index 7a487482d3..485dbd7ef0 100644
--- a/lib/cretonne/meta/isa/riscv/defs.py
+++ b/lib/cretonne/meta/isa/riscv/defs.py
@@ -7,8 +7,8 @@ from __future__ import absolute_import
 from cdsl.isa import TargetISA, CPUMode
 import base.instructions
 
-isa = TargetISA('riscv', [base.instructions.GROUP])
+ISA = TargetISA('riscv', [base.instructions.GROUP])
 
 # CPU modes for 32-bit and 64-bit operation.
-RV32 = CPUMode('RV32', isa)
-RV64 = CPUMode('RV64', isa)
+RV32 = CPUMode('RV32', ISA)
+RV64 = CPUMode('RV64', ISA)
diff --git a/lib/cretonne/meta/isa/riscv/settings.py b/lib/cretonne/meta/isa/riscv/settings.py
index 7571bf1611..e6fe230f89 100644
--- a/lib/cretonne/meta/isa/riscv/settings.py
+++ b/lib/cretonne/meta/isa/riscv/settings.py
@@ -5,9 +5,9 @@ from __future__ import absolute_import
 from cdsl.settings import SettingGroup, BoolSetting
 from cdsl.predicates import And
 import base.settings as shared
-from .defs import isa
+from .defs import ISA
 
-isa.settings = SettingGroup('riscv', parent=shared.group)
+ISA.settings = SettingGroup('riscv', parent=shared.group)
 
 supports_m = BoolSetting("CPU supports the 'M' extension (mul/div)")
 supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
@@ -25,4 +25,4 @@ use_d = And(supports_d, shared.enable_float)
 
 full_float = And(shared.enable_simd, supports_f, supports_d)
 
-isa.settings.close(globals())
+ISA.settings.close(globals())