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[meta] Remove mentions to Python in comments of the non-meta crate;

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This commit is contained in:
Benjamin Bouvier
2019-06-20 18:42:23 +02:00
parent f29a26de14
commit 563525b090
17 changed files with 39 additions and 40 deletions
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8
cranelift/codegen/src/isa/registers.rs
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@@ -17,19 +17,19 @@ pub type RegUnit = u16;
/// The size of this type is determined by the target ISA that has the most register units defined.
/// Currently that is arm32 which has 64+16 units.
///
/// This type should be coordinated with meta-python/cdsl/registers.py.
/// This type should be coordinated with meta/src/cdsl/regs.rs.
pub type RegUnitMask = [u32; 3];
/// A bit mask indexed by register classes.
///
/// The size of this type is determined by the ISA with the most register classes.
///
/// This type should be coordinated with meta-python/cdsl/isa.py.
/// This type should be coordinated with meta/src/cdsl/regs.rs.
pub type RegClassMask = u32;
/// Guaranteed maximum number of top-level register classes with pressure tracking in any ISA.
///
/// This can be increased, but should be coordinated with meta-python/cdsl/isa.py.
/// This can be increased, but should be coordinated with meta/src/cdsl/regs.rs.
pub const MAX_TRACKED_TOPRCS: usize = 4;
/// The register units in a target ISA are divided into disjoint register banks. Each bank covers a
@@ -37,7 +37,7 @@ pub const MAX_TRACKED_TOPRCS: usize = 4;
///
/// The `RegBank` struct provides a static description of a register bank.
pub struct RegBank {
/// The name of this register bank as defined in the ISA's `registers.py` file.
/// The name of this register bank as defined in the ISA's DSL definition.
pub name: &'static str,
/// The first register unit in this bank.