aarch64: Use smaller instruction helpers in ISLE (#3618)
* aarch64: Use smaller instruction helpers in ISLE This commit moves the aarch64 backend's ISLE to be more similar to the x64 backend's ISLE where one-liner instruction builders are used for various forms of instructions instead of always using the constructor-per-variant-of-`Inst`. Overall I think this change worked out quite well and sets up some naming idioms as well for various forms of instructions. * rebase conflict
This commit is contained in:
Alex Crichton
@@ -1582,6 +1582,307 @@
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(ConsumesFlags.ConsumesFlags (MInst.CSel dst cond if_true if_false)
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(writable_reg_to_reg dst))))
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;; Helpers for generating `add` instructions.
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(decl add (Type Reg Reg) Reg)
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(rule (add (fits_in_32 _ty) x y) (add32 x y))
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(rule (add $I64 x y) (add64 x y))
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(decl add32 (Reg Reg) Reg)
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(rule (add32 x y) (alu_rrr (ALUOp.Add32) x y))
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(decl add64 (Reg Reg) Reg)
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(rule (add64 x y) (alu_rrr (ALUOp.Add64) x y))
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(decl add_imm (Type Reg Imm12) Reg)
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(rule (add_imm (fits_in_32 _ty) x y) (add32_imm x y))
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(rule (add_imm $I64 x y) (add64_imm x y))
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(decl add32_imm (Reg Imm12) Reg)
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(rule (add32_imm x y) (alu_rr_imm12 (ALUOp.Add32) x y))
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(decl add64_imm (Reg Imm12) Reg)
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(rule (add64_imm x y) (alu_rr_imm12 (ALUOp.Add64) x y))
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(decl add_extend (Type Reg ExtendedValue) Reg)
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(rule (add_extend (fits_in_32 _ty) x y) (add32_extend x y))
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(rule (add_extend $I64 x y) (add64_extend x y))
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(decl add32_extend (Reg ExtendedValue) Reg)
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(rule (add32_extend x y) (alu_rr_extend_reg (ALUOp.Add32) x y))
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(decl add64_extend (Reg ExtendedValue) Reg)
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(rule (add64_extend x y) (alu_rr_extend_reg (ALUOp.Add64) x y))
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(decl add_shift (Type Reg Reg ShiftOpAndAmt) Reg)
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(rule (add_shift (fits_in_32 _ty) x y z) (add32_shift x y z))
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(rule (add_shift $I64 x y z) (add64_shift x y z))
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(decl add32_shift (Reg Reg ShiftOpAndAmt) Reg)
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(rule (add32_shift x y z) (alu_rrr_shift (ALUOp.Add32) x y z))
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(decl add64_shift (Reg Reg ShiftOpAndAmt) Reg)
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(rule (add64_shift x y z) (alu_rrr_shift (ALUOp.Add64) x y z))
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(decl add_vec (Reg Reg VectorSize) Reg)
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(rule (add_vec x y size) (vec_rrr (VecALUOp.Add) x y size))
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;; Helpers for generating `sub` instructions.
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(decl sub (Type Reg Reg) Reg)
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(rule (sub (fits_in_32 _ty) x y) (sub32 x y))
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(rule (sub $I64 x y) (sub64 x y))
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(decl sub32 (Reg Reg) Reg)
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(rule (sub32 x y) (alu_rrr (ALUOp.Sub32) x y))
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(decl sub64 (Reg Reg) Reg)
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(rule (sub64 x y) (alu_rrr (ALUOp.Sub64) x y))
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(decl sub_imm (Type Reg Imm12) Reg)
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(rule (sub_imm (fits_in_32 _ty) x y) (sub32_imm x y))
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(rule (sub_imm $I64 x y) (sub64_imm x y))
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(decl sub32_imm (Reg Imm12) Reg)
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(rule (sub32_imm x y) (alu_rr_imm12 (ALUOp.Sub32) x y))
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(decl sub64_imm (Reg Imm12) Reg)
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(rule (sub64_imm x y) (alu_rr_imm12 (ALUOp.Sub64) x y))
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(decl sub_extend (Type Reg ExtendedValue) Reg)
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(rule (sub_extend (fits_in_32 _ty) x y) (sub32_extend x y))
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(rule (sub_extend $I64 x y) (sub64_extend x y))
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(decl sub32_extend (Reg ExtendedValue) Reg)
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(rule (sub32_extend x y) (alu_rr_extend_reg (ALUOp.Sub32) x y))
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(decl sub64_extend (Reg ExtendedValue) Reg)
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(rule (sub64_extend x y) (alu_rr_extend_reg (ALUOp.Sub64) x y))
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(decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
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(rule (sub_shift (fits_in_32 _ty) x y z) (sub32_shift x y z))
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(rule (sub_shift $I64 x y z) (sub64_shift x y z))
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(decl sub32_shift (Reg Reg ShiftOpAndAmt) Reg)
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(rule (sub32_shift x y z) (alu_rrr_shift (ALUOp.Sub32) x y z))
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(decl sub64_shift (Reg Reg ShiftOpAndAmt) Reg)
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(rule (sub64_shift x y z) (alu_rrr_shift (ALUOp.Sub64) x y z))
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(decl sub_vec (Reg Reg VectorSize) Reg)
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(rule (sub_vec x y size) (vec_rrr (VecALUOp.Sub) x y size))
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;; Helpers for generating `madd` instructions.
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(decl madd (Type Reg Reg Reg) Reg)
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(rule (madd (fits_in_32 _ty) x y z) (madd32 x y z))
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(rule (madd $I64 x y z) (madd64 x y z))
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(decl madd32 (Reg Reg Reg) Reg)
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(rule (madd32 x y z) (alu_rrrr (ALUOp3.MAdd32) x y z))
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(decl madd64 (Reg Reg Reg) Reg)
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(rule (madd64 x y z) (alu_rrrr (ALUOp3.MAdd64) x y z))
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;; Helpers for generating `msub` instructions.
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(decl msub64 (Reg Reg Reg) Reg)
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(rule (msub64 x y z) (alu_rrrr (ALUOp3.MSub64) x y z))
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;; Helper for generating `uqadd` instructions.
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(decl uqadd (Reg Reg VectorSize) Reg)
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(rule (uqadd x y size) (vec_rrr (VecALUOp.Uqadd) x y size))
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;; Helper for generating `sqadd` instructions.
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(decl sqadd (Reg Reg VectorSize) Reg)
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(rule (sqadd x y size) (vec_rrr (VecALUOp.Sqadd) x y size))
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;; Helper for generating `uqsub` instructions.
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(decl uqsub (Reg Reg VectorSize) Reg)
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(rule (uqsub x y size) (vec_rrr (VecALUOp.Uqsub) x y size))
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;; Helper for generating `sqsub` instructions.
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(decl sqsub (Reg Reg VectorSize) Reg)
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(rule (sqsub x y size) (vec_rrr (VecALUOp.Sqsub) x y size))
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;; Helper for generating `umulh` instructions.
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(decl umulh (Reg Reg) Reg)
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(rule (umulh x y) (alu_rrr (ALUOp.UMulH) x y))
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;; Helper for generating `smulh` instructions.
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(decl smulh (Reg Reg) Reg)
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(rule (smulh x y) (alu_rrr (ALUOp.SMulH) x y))
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;; Helper for generating `mul` instructions.
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(decl mul (Reg Reg VectorSize) Reg)
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(rule (mul x y size) (vec_rrr (VecALUOp.Mul) x y size))
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;; Helper for generating `neg` instructions.
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(decl neg (Reg VectorSize) Reg)
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(rule (neg x size) (vec_misc (VecMisc2.Neg) x size))
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;; Helper for generating `rev64` instructions.
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(decl rev64 (Reg VectorSize) Reg)
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(rule (rev64 x size) (vec_misc (VecMisc2.Rev64) x size))
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;; Helper for generating `xtn64` instructions.
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(decl xtn64 (Reg bool) Reg)
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(rule (xtn64 x high_half) (vec_rr_narrow (VecRRNarrowOp.Xtn64) x high_half))
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;; Helper for generating `addp` instructions.
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(decl addp (Reg Reg VectorSize) Reg)
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(rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))
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;; Helper for generating `shll32` instructions.
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(decl shll32 (Reg bool) Reg)
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(rule (shll32 x high_half) (vec_rr_long (VecRRLongOp.Shll32) x high_half))
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;; Helper for generating `umlal32` instructions.
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(decl umlal32 (Reg Reg Reg bool) Reg)
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(rule (umlal32 x y z high_half) (vec_rrrr_long (VecRRRLongOp.Umlal32) x y z high_half))
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;; Helper for generating `smull8` instructions.
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(decl smull8 (Reg Reg bool) Reg)
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(rule (smull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull8) x y high_half))
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;; Helper for generating `umull8` instructions.
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(decl umull8 (Reg Reg bool) Reg)
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(rule (umull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull8) x y high_half))
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;; Helper for generating `smull16` instructions.
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(decl smull16 (Reg Reg bool) Reg)
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(rule (smull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull16) x y high_half))
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;; Helper for generating `umull16` instructions.
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(decl umull16 (Reg Reg bool) Reg)
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(rule (umull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull16) x y high_half))
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;; Helper for generating `smull32` instructions.
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(decl smull32 (Reg Reg bool) Reg)
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(rule (smull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull32) x y high_half))
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;; Helper for generating `umull32` instructions.
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(decl umull32 (Reg Reg bool) Reg)
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(rule (umull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull32) x y high_half))
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;; Helper for generating `asr` instructions.
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(decl asr64 (Reg Reg) Reg)
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(rule (asr64 x y) (alu_rrr (ALUOp.Asr64) x y))
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(decl asr64_imm (Reg ImmShift) Reg)
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(rule (asr64_imm x imm) (alu_rr_imm_shift (ALUOp.Asr64) x imm))
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;; Helper for generating `lsr` instructions.
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(decl lsr32 (Reg Reg) Reg)
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(rule (lsr32 x y) (alu_rrr (ALUOp.Lsr32) x y))
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(decl lsr32_imm (Reg ImmShift) Reg)
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(rule (lsr32_imm x imm) (alu_rr_imm_shift (ALUOp.Lsr32) x imm))
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(decl lsr64 (Reg Reg) Reg)
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(rule (lsr64 x y) (alu_rrr (ALUOp.Lsr64) x y))
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(decl lsr64_imm (Reg ImmShift) Reg)
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(rule (lsr64_imm x imm) (alu_rr_imm_shift (ALUOp.Lsr64) x imm))
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;; Helper for generating `lsl` instructions.
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(decl lsl32 (Reg Reg) Reg)
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(rule (lsl32 x y) (alu_rrr (ALUOp.Lsl32) x y))
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(decl lsl32_imm (Reg ImmShift) Reg)
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(rule (lsl32_imm x imm) (alu_rr_imm_shift (ALUOp.Lsl32) x imm))
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(decl lsl64 (Reg Reg) Reg)
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(rule (lsl64 x y) (alu_rrr (ALUOp.Lsl64) x y))
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(decl lsl64_imm (Reg ImmShift) Reg)
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(rule (lsl64_imm x imm) (alu_rr_imm_shift (ALUOp.Lsl64) x imm))
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;; Helper for generating `udiv` instructions.
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(decl udiv64 (Reg Reg) Reg)
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(rule (udiv64 x y) (alu_rrr (ALUOp.UDiv64) x y))
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;; Helper for generating `sdiv` instructions.
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(decl sdiv64 (Reg Reg) Reg)
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(rule (sdiv64 x y) (alu_rrr (ALUOp.SDiv64) x y))
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;; Helper for generating `not` instructions.
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(decl not (Reg VectorSize) Reg)
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(rule (not x size) (vec_misc (VecMisc2.Not) x size))
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;; Helpers for generating `orr_not` instructions.
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(decl orr_not (Type Reg Reg) Reg)
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(rule (orr_not (fits_in_32 _ty) x y) (orr_not32 x y))
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(rule (orr_not $I64 x y) (orr_not64 x y))
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(decl orr_not32 (Reg Reg) Reg)
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(rule (orr_not32 x y) (alu_rrr (ALUOp.OrrNot32) x y))
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(decl orr_not64 (Reg Reg) Reg)
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(rule (orr_not64 x y) (alu_rrr (ALUOp.OrrNot64) x y))
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(decl orr_not_shift (Type Reg Reg ShiftOpAndAmt) Reg)
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(rule (orr_not_shift (fits_in_32 _ty) x y shift) (orr_not_shift32 x y shift))
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(rule (orr_not_shift $I64 x y shift) (orr_not_shift64 x y shift))
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(decl orr_not_shift32 (Reg Reg ShiftOpAndAmt) Reg)
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(rule (orr_not_shift32 x y shift) (alu_rrr_shift (ALUOp.OrrNot32) x y shift))
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(decl orr_not_shift64 (Reg Reg ShiftOpAndAmt) Reg)
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(rule (orr_not_shift64 x y shift) (alu_rrr_shift (ALUOp.OrrNot64) x y shift))
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;; Helpers for generating `orr` instructions.
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(decl orr32 (Reg Reg) Reg)
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(rule (orr32 x y) (alu_rrr (ALUOp.Orr32) x y))
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(decl orr64 (Reg Reg) Reg)
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(rule (orr64 x y) (alu_rrr (ALUOp.Orr64) x y))
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(decl orr64_imm (Reg ImmLogic) Reg)
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(rule (orr64_imm x y) (alu_rr_imm_logic (ALUOp.Orr64) x y))
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(decl orr_vec (Reg Reg VectorSize) Reg)
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(rule (orr_vec x y size) (vec_rrr (VecALUOp.Orr) x y size))
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;; Helpers for generating `and` instructions.
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(decl and32_imm (Reg ImmLogic) Reg)
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(rule (and32_imm x y) (alu_rr_imm_logic (ALUOp.And32) x y))
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(decl and_vec (Reg Reg VectorSize) Reg)
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(rule (and_vec x y size) (vec_rrr (VecALUOp.And) x y size))
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;; Helpers for generating `eor` instructions.
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(decl eor_vec (Reg Reg VectorSize) Reg)
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(rule (eor_vec x y size) (vec_rrr (VecALUOp.Eor) x y size))
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;; Helpers for generating `bic` instructions.
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(decl bic_vec (Reg Reg VectorSize) Reg)
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(rule (bic_vec x y size) (vec_rrr (VecALUOp.Bic) x y size))
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;; Helpers for generating `sshl` instructions.
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(decl sshl (Reg Reg VectorSize) Reg)
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(rule (sshl x y size) (vec_rrr (VecALUOp.Sshl) x y size))
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;; Helpers for generating `ushl` instructions.
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(decl ushl (Reg Reg VectorSize) Reg)
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(rule (ushl x y size) (vec_rrr (VecALUOp.Ushl) x y size))
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;; Helpers for generating `rotr` instructions.
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(decl rotr32 (Reg Reg) Reg)
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(rule (rotr32 x y) (alu_rrr (ALUOp.RotR32) x y))
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(decl rotr32_imm (Reg ImmShift) Reg)
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(rule (rotr32_imm x y) (alu_rr_imm_shift (ALUOp.RotR32) x y))
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(decl rotr64 (Reg Reg) Reg)
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(rule (rotr64 x y) (alu_rrr (ALUOp.RotR64) x y))
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(decl rotr64_imm (Reg ImmShift) Reg)
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(rule (rotr64_imm x y) (alu_rr_imm_shift (ALUOp.RotR64) x y))
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;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1597,7 +1898,7 @@
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;; Weird logical-instruction immediate in ORI using zero register
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(rule (imm (integral_ty _ty) (imm_logic_from_u64 <$I64 n))
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(alu_rr_imm_logic (ALUOp.Orr64) (zero_reg) n))
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(orr64_imm (zero_reg) n))
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(decl load_constant64_full (u64) Reg)
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(extern constructor load_constant64_full load_constant64_full)
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