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Merge pull request #3126 from jlb6740/int-to-int-extend

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Add x64 support for remaining int-to-int extend simd instructions
This commit is contained in:
Chris Fallin
2021-07-29 09:49:22 -07:00
committed by GitHub
parent 072d5dc978 4f601edc36
commit 535b3a47ee
2 changed files with 27 additions and 5 deletions
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1
build.rs
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@@ -192,7 +192,6 @@ fn x64_should_panic(testsuite: &str, testname: &str, strategy: &str) -> bool {
match (testsuite, testname) { match (testsuite, testname) {
("simd", "simd_i16x8_extadd_pairwise_i8x16") => return true, ("simd", "simd_i16x8_extadd_pairwise_i8x16") => return true,
("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true, ("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true,
("simd", "simd_int_to_int_extend") => return true,
("simd", _) => return false, ("simd", _) => return false,
_ => {} _ => {}
} }

31
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -4941,6 +4941,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
(types::I16X8, types::I32X4) => { (types::I16X8, types::I32X4) => {
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(src), dst)); ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(src), dst));
} }
(types::I32X4, types::I64X2) => {
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::reg(src), dst));
}
_ => unreachable!(), _ => unreachable!(),
}, },
Opcode::SwidenHigh => match (input_ty, output_ty) { Opcode::SwidenHigh => match (input_ty, output_ty) {
@@ -4966,6 +4969,16 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
)); ));
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::from(dst), dst)); ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::from(dst), dst));
} }
(types::I32X4, types::I64X2) => {
ctx.emit(Inst::xmm_rm_r_imm(
SseOpcode::Pshufd,
RegMem::reg(src),
dst,
0xEE,
OperandSize::Size32,
));
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::from(dst), dst));
}
_ => unreachable!(), _ => unreachable!(),
}, },
Opcode::UwidenLow => match (input_ty, output_ty) { Opcode::UwidenLow => match (input_ty, output_ty) {
@@ -4975,10 +4988,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
(types::I16X8, types::I32X4) => { (types::I16X8, types::I32X4) => {
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(src), dst)); ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(src), dst));
} }
_ => unreachable!( (types::I32X4, types::I64X2) => {
"In UwidenLow: input_ty {:?}, output_ty {:?}", ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::reg(src), dst));
input_ty, output_ty }
), _ => unreachable!(),
}, },
Opcode::UwidenHigh => match (input_ty, output_ty) { Opcode::UwidenHigh => match (input_ty, output_ty) {
(types::I8X16, types::I16X8) => { (types::I8X16, types::I16X8) => {
@@ -5003,6 +5016,16 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
)); ));
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::from(dst), dst)); ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::from(dst), dst));
} }
(types::I32X4, types::I64X2) => {
ctx.emit(Inst::xmm_rm_r_imm(
SseOpcode::Pshufd,
RegMem::reg(src),
dst,
0xEE,
OperandSize::Size32,
));
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::from(dst), dst));
}
_ => unreachable!(), _ => unreachable!(),
}, },
_ => unreachable!(), _ => unreachable!(),