riscv64: Fix masking on iabs (#5505)
* cranelift: Add `iabs.i128` runtest * riscv64: Fix incorrect extension in iabs When lowering iabs, we were accidentally comparing the unextended value this caused the instruction to misbehave with certain top bits. This commit also adds a zbb lowering that does not use jumps.
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@@ -2011,9 +2011,13 @@
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(step WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.Rev8 rs step tmp rd))))
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(writable_reg_to_reg rd)))
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(decl pure has_zbkb () bool)
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(extern constructor has_zbkb has_zbkb)
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(decl pure has_zbb () bool)
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(extern constructor has_zbb has_zbb)
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(decl gen_brev8 (Reg Type) Reg)
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(rule 1
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(gen_brev8 rs _)
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@@ -2038,14 +2042,41 @@
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((tmp Reg (gen_bit_not y)))
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(alu_rrr (AluOPRRR.Xor) x tmp)))
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(decl lower_iabs (Reg Type) Reg)
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(rule
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(lower_iabs r ty)
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(let
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((tmp Reg (ext_int_if_need $true r ty))
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(a Reg (gen_bit_not r))
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(a2 Reg (alu_rr_imm12 (AluOPRRI.Addi) a (imm12_const 1))))
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(gen_select_reg (IntCC.SignedLessThan) r (zero_reg) a2 r)))
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;; Negates x
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;; Equivalent to 0 - x
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(decl neg (Type ValueRegs) ValueRegs)
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(rule 1 (neg (fits_in_64 (ty_int ty)) val)
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(value_reg
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(alu_rrr (AluOPRRR.Sub) (zero_reg) (value_regs_get val 0))))
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(rule 2 (neg $I128 val)
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(i128_sub (value_regs_zero) val))
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;; Selects the greatest of two registers as signed values.
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(decl max (Type Reg Reg) Reg)
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(rule (max (fits_in_64 (ty_int ty)) x y)
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(if-let $true (has_zbb))
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(alu_rrr (AluOPRRR.Max) x y))
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(rule (max (fits_in_64 (ty_int ty)) x y)
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(if-let $false (has_zbb))
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(gen_select_reg (IntCC.SignedGreaterThan) x y x y))
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(decl lower_iabs (Type Reg) Reg)
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; I64 and lower
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; Generate the following code:
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; sext.{b,h,w} a0, a0
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; neg a1, a0
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; max a0, a0, a1
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(rule (lower_iabs (fits_in_64 ty) val)
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(let ((extended Reg (ext_int_if_need $true val ty))
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(negated Reg (neg $I64 extended)))
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(max $I64 extended negated)))
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(decl gen_trapff (FloatCC Reg Reg Type TrapCode) InstOutput)
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(rule
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