diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index afdab0d2a4..e58a7d9894 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -72,6 +72,7 @@ use alloc::vec::Vec; use regalloc::{RealReg, Reg, RegClass, Set, SpillSlot, Writable}; +use core::mem; use log::{debug, trace}; /// A location for an argument or return value. @@ -1267,8 +1268,11 @@ impl ABICall for AArch64ABICall { } } - fn emit_call>(&self, ctx: &mut C) { - let (uses, defs) = (self.uses.clone(), self.defs.clone()); + fn emit_call>(&mut self, ctx: &mut C) { + let (uses, defs) = ( + mem::replace(&mut self.uses, Set::empty()), + mem::replace(&mut self.defs, Set::empty()), + ); match &self.dest { &CallDest::ExtName(ref name, RelocDistance::Near) => ctx.emit(Inst::Call { dest: name.clone(), diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs index f27a5166ee..d00a0b464e 100644 --- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs +++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs @@ -1263,7 +1263,7 @@ pub(crate) fn lower_insn_to_regs>(ctx: &mut C, insn: IRIns Opcode::Call | Opcode::CallIndirect => { let loc = ctx.srcloc(insn); - let (abi, inputs) = match op { + let (mut abi, inputs) = match op { Opcode::Call => { let (extname, dist) = ctx.call_target(insn).unwrap(); let extname = extname.clone(); diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index ae04e127cf..0ccfad2e36 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -167,5 +167,5 @@ pub trait ABICall { /// registers are also logically defs, but should never be read; their /// values are "defined" (to the regalloc) but "undefined" in every other /// sense.) - fn emit_call>(&self, ctx: &mut C); + fn emit_call>(&mut self, ctx: &mut C); }