From 51dea9f78457c04fbeb3a2a86e25392dc8a2a442 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 10 Apr 2017 10:28:37 -0700 Subject: [PATCH] Syntax tweak: Omit comma after an initial enum immediate. This affects the comparison instructions which now read "icmp ult a, b". This mimics LLVM's style and makes it simpler to add instruction flags in the future, such as "load v1" -> "load aligned v1". These enumerated operands and flags feel like opcode modifiers rather than value operands, so displaying them differently makes sense. Value and numeric operands are still comma separated. --- cranelift/filetests/cfg/loop.cton | 2 +- cranelift/filetests/isa/riscv/binary32.cton | 40 +++++++++---------- cranelift/filetests/isa/riscv/expand-i32.cton | 2 +- .../filetests/isa/riscv/legalize-i64.cton | 2 +- cranelift/filetests/parser/tiny.cton | 28 ++++++------- lib/cretonne/src/write.rs | 8 ++-- lib/reader/src/parser.rs | 4 -- 7 files changed, 41 insertions(+), 45 deletions(-) diff --git a/cranelift/filetests/cfg/loop.cton b/cranelift/filetests/cfg/loop.cton index 9a1ca6d7e3..3f7892a9d9 100644 --- a/cranelift/filetests/cfg/loop.cton +++ b/cranelift/filetests/cfg/loop.cton @@ -21,7 +21,7 @@ ebb1(v5: i32): v10 = f32const 0.0 v11 = fadd v9, v10 v12 = iadd_imm v5, 1 - v13 = icmp ult, v12, v2 + v13 = icmp ult v12, v2 brnz v13, ebb1(v12) ; unordered: ebb1:inst12 -> ebb1 v14 = f64const 0.0 v15 = f64const 0.0 diff --git a/cranelift/filetests/isa/riscv/binary32.cton b/cranelift/filetests/isa/riscv/binary32.cton index d34fe34e21..89771d8165 100644 --- a/cranelift/filetests/isa/riscv/binary32.cton +++ b/cranelift/filetests/isa/riscv/binary32.cton @@ -33,11 +33,11 @@ ebb0: [-,%x7] v34 = sshr v1, v2 ; bin: 415553b3 [-,%x16] v35 = sshr v2, v1 ; bin: 40aad833 ; slt - [-,%x7] v42 = icmp slt, v1, v2 ; bin: 015523b3 - [-,%x16] v43 = icmp slt, v2, v1 ; bin: 00aaa833 + [-,%x7] v42 = icmp slt v1, v2 ; bin: 015523b3 + [-,%x16] v43 = icmp slt v2, v1 ; bin: 00aaa833 ; sltu - [-,%x7] v44 = icmp ult, v1, v2 ; bin: 015533b3 - [-,%x16] v45 = icmp ult, v2, v1 ; bin: 00aab833 + [-,%x7] v44 = icmp ult v1, v2 ; bin: 015533b3 + [-,%x16] v45 = icmp ult v2, v1 ; bin: 00aab833 ; Integer Register-Immediate Instructions @@ -65,11 +65,11 @@ ebb0: [-,%x16] v125 = sshr_imm v2, 8 ; bin: 408ad813 ; slti - [-,%x7] v130 = icmp_imm slt, v1, 1000 ; bin: 3e852393 - [-,%x16] v131 = icmp_imm slt, v2, -905 ; bin: c77aa813 + [-,%x7] v130 = icmp_imm slt v1, 1000 ; bin: 3e852393 + [-,%x16] v131 = icmp_imm slt v2, -905 ; bin: c77aa813 ; sltiu - [-,%x7] v132 = icmp_imm ult, v1, 1000 ; bin: 3e853393 - [-,%x16] v133 = icmp_imm ult, v2, -905 ; bin: c77ab813 + [-,%x7] v132 = icmp_imm ult v1, 1000 ; bin: 3e853393 + [-,%x16] v133 = icmp_imm ult v2, -905 ; bin: c77ab813 ; lui [-,%x7] v140 = iconst.i32 0x12345000 ; bin: 123453b7 @@ -82,31 +82,31 @@ ebb0: ebb1: ; beq 0x000 - br_icmp eq, v1, v2, ebb1 ; bin: 01550063 + br_icmp eq v1, v2, ebb1 ; bin: 01550063 ; bne 0xffc - br_icmp ne, v1, v2, ebb1 ; bin: ff551ee3 + br_icmp ne v1, v2, ebb1 ; bin: ff551ee3 ; blt 0xff8 - br_icmp slt, v1, v2, ebb1 ; bin: ff554ce3 + br_icmp slt v1, v2, ebb1 ; bin: ff554ce3 ; bge 0xff4 - br_icmp sge, v1, v2, ebb1 ; bin: ff555ae3 + br_icmp sge v1, v2, ebb1 ; bin: ff555ae3 ; bltu 0xff0 - br_icmp ult, v1, v2, ebb1 ; bin: ff5568e3 + br_icmp ult v1, v2, ebb1 ; bin: ff5568e3 ; bgeu 0xfec - br_icmp uge, v1, v2, ebb1 ; bin: ff5576e3 + br_icmp uge v1, v2, ebb1 ; bin: ff5576e3 ; Forward branches. ; beq 0x018 - br_icmp eq, v2, v1, ebb2 ; bin: 00aa8c63 + br_icmp eq v2, v1, ebb2 ; bin: 00aa8c63 ; bne 0x014 - br_icmp ne, v2, v1, ebb2 ; bin: 00aa9a63 + br_icmp ne v2, v1, ebb2 ; bin: 00aa9a63 ; blt 0x010 - br_icmp slt, v2, v1, ebb2 ; bin: 00aac863 + br_icmp slt v2, v1, ebb2 ; bin: 00aac863 ; bge 0x00c - br_icmp sge, v2, v1, ebb2 ; bin: 00aad663 + br_icmp sge v2, v1, ebb2 ; bin: 00aad663 ; bltu 0x008 - br_icmp ult, v2, v1, ebb2 ; bin: 00aae463 + br_icmp ult v2, v1, ebb2 ; bin: 00aae463 ; bgeu 0x004 - br_icmp uge, v2, v1, ebb2 ; bin: 00aaf263 + br_icmp uge v2, v1, ebb2 ; bin: 00aaf263 fallthrough ebb2 diff --git a/cranelift/filetests/isa/riscv/expand-i32.cton b/cranelift/filetests/isa/riscv/expand-i32.cton index 166b058eb2..0415c6026c 100644 --- a/cranelift/filetests/isa/riscv/expand-i32.cton +++ b/cranelift/filetests/isa/riscv/expand-i32.cton @@ -15,7 +15,7 @@ ebb0(v1: i32, v2: i32): return v3, v4 } ; check: $v3 = iadd $v1, $v2 -; check: $(cout=$V) = icmp ult, $v3, $v1 +; check: $(cout=$V) = icmp ult $v3, $v1 ; It's possible the legalizer will rewrite these value aliases in the future. ; check: $v4 -> $cout ; check: return $v3, $v4 diff --git a/cranelift/filetests/isa/riscv/legalize-i64.cton b/cranelift/filetests/isa/riscv/legalize-i64.cton index e2d5a763a2..dbe26f824c 100644 --- a/cranelift/filetests/isa/riscv/legalize-i64.cton +++ b/cranelift/filetests/isa/riscv/legalize-i64.cton @@ -54,7 +54,7 @@ ebb0(v1: i64, v2: i64): ; check: $ebb0($(v1l=$V): i32, $(v1h=$V): i32, $(v2l=$V): i32, $(v2h=$V): i32): ; check: [R#0c ; sameln: $(v3l=$V) = iadd $v1l, $v2l -; check: $(c=$V) = icmp ult, $v3l, $v1l +; check: $(c=$V) = icmp ult $v3l, $v1l ; check: [R#0c ; sameln: $(v3h1=$V) = iadd $v1h, $v2h ; check: $(c_int=$V) = bint.i32 $c diff --git a/cranelift/filetests/parser/tiny.cton b/cranelift/filetests/parser/tiny.cton index d5790c0e89..21d3a59815 100644 --- a/cranelift/filetests/parser/tiny.cton +++ b/cranelift/filetests/parser/tiny.cton @@ -52,33 +52,33 @@ ebb0: ; Integer condition codes. function icmp(i32, i32) { ebb0(vx0: i32, vx1: i32): - v0 = icmp eq, vx0, vx1 - v1 = icmp ult, vx0, vx1 - v2 = icmp_imm sge, vx0, -12 + v0 = icmp eq vx0, vx1 + v1 = icmp ult vx0, vx1 + v2 = icmp_imm sge vx0, -12 v3 = irsub_imm vx1, 45 - br_icmp eq, vx0, vx1, ebb0(vx1, vx0) + br_icmp eq vx0, vx1, ebb0(vx1, vx0) } ; sameln: function icmp(i32, i32) { ; nextln: ebb0(vx0: i32, vx1: i32): -; nextln: v0 = icmp eq, vx0, vx1 -; nextln: v1 = icmp ult, vx0, vx1 -; nextln: v2 = icmp_imm sge, vx0, -12 +; nextln: v0 = icmp eq vx0, vx1 +; nextln: v1 = icmp ult vx0, vx1 +; nextln: v2 = icmp_imm sge vx0, -12 ; nextln: v3 = irsub_imm vx1, 45 -; nextln: br_icmp eq, vx0, vx1, ebb0(vx1, vx0) +; nextln: br_icmp eq vx0, vx1, ebb0(vx1, vx0) ; nextln: } ; Floating condition codes. function fcmp(f32, f32) { ebb0(vx0: f32, vx1: f32): - v0 = fcmp eq, vx0, vx1 - v1 = fcmp uno, vx0, vx1 - v2 = fcmp lt, vx0, vx1 + v0 = fcmp eq vx0, vx1 + v1 = fcmp uno vx0, vx1 + v2 = fcmp lt vx0, vx1 } ; sameln: function fcmp(f32, f32) { ; nextln: ebb0(vx0: f32, vx1: f32): -; nextln: v0 = fcmp eq, vx0, vx1 -; nextln: v1 = fcmp uno, vx0, vx1 -; nextln: v2 = fcmp lt, vx0, vx1 +; nextln: v0 = fcmp eq vx0, vx1 +; nextln: v1 = fcmp uno vx0, vx1 +; nextln: v2 = fcmp lt vx0, vx1 ; nextln: } ; The bitcast instruction has two type variables: The controlling type variable diff --git a/lib/cretonne/src/write.rs b/lib/cretonne/src/write.rs index 7dfe743ead..eaa5248408 100644 --- a/lib/cretonne/src/write.rs +++ b/lib/cretonne/src/write.rs @@ -259,9 +259,9 @@ pub fn write_operands(w: &mut Write, dfg: &DataFlowGraph, inst: Inst) -> Result } InsertLane { lane, args, .. } => write!(w, " {}, {}, {}", args[0], lane, args[1]), ExtractLane { lane, arg, .. } => write!(w, " {}, {}", arg, lane), - IntCompare { cond, args, .. } => write!(w, " {}, {}, {}", cond, args[0], args[1]), - IntCompareImm { cond, arg, imm, .. } => write!(w, " {}, {}, {}", cond, arg, imm), - FloatCompare { cond, args, .. } => write!(w, " {}, {}, {}", cond, args[0], args[1]), + IntCompare { cond, args, .. } => write!(w, " {} {}, {}", cond, args[0], args[1]), + IntCompareImm { cond, arg, imm, .. } => write!(w, " {} {}, {}", cond, arg, imm), + FloatCompare { cond, args, .. } => write!(w, " {} {}, {}", cond, args[0], args[1]), Jump { destination, ref args, @@ -295,7 +295,7 @@ pub fn write_operands(w: &mut Write, dfg: &DataFlowGraph, inst: Inst) -> Result .. } => { let args = args.as_slice(pool); - write!(w, " {}, {}, {}, {}", cond, args[0], args[1], destination)?; + write!(w, " {} {}, {}, {}", cond, args[0], args[1], destination)?; if args.len() > 2 { write!(w, "({})", DisplayValues(&args[2..]))?; } diff --git a/lib/reader/src/parser.rs b/lib/reader/src/parser.rs index 1843c78776..b9ee4acd58 100644 --- a/lib/reader/src/parser.rs +++ b/lib/reader/src/parser.rs @@ -1526,7 +1526,6 @@ impl<'a> Parser<'a> { } InstructionFormat::BranchIcmp => { let cond = self.match_enum("expected intcc condition code")?; - self.match_token(Token::Comma, "expected ',' between operands")?; let lhs = self.match_value("expected SSA value first operand")?; self.match_token(Token::Comma, "expected ',' between operands")?; let rhs = self.match_value("expected SSA value second operand")?; @@ -1567,7 +1566,6 @@ impl<'a> Parser<'a> { } InstructionFormat::IntCompare => { let cond = self.match_enum("expected intcc condition code")?; - self.match_token(Token::Comma, "expected ',' between operands")?; let lhs = self.match_value("expected SSA value first operand")?; self.match_token(Token::Comma, "expected ',' between operands")?; let rhs = self.match_value("expected SSA value second operand")?; @@ -1580,7 +1578,6 @@ impl<'a> Parser<'a> { } InstructionFormat::IntCompareImm => { let cond = self.match_enum("expected intcc condition code")?; - self.match_token(Token::Comma, "expected ',' between operands")?; let lhs = self.match_value("expected SSA value first operand")?; self.match_token(Token::Comma, "expected ',' between operands")?; let rhs = self.match_imm64("expected immediate second operand")?; @@ -1594,7 +1591,6 @@ impl<'a> Parser<'a> { } InstructionFormat::FloatCompare => { let cond = self.match_enum("expected floatcc condition code")?; - self.match_token(Token::Comma, "expected ',' between operands")?; let lhs = self.match_value("expected SSA value first operand")?; self.match_token(Token::Comma, "expected ',' between operands")?; let rhs = self.match_value("expected SSA value second operand")?;