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Implement vector element extensions for AArch64

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This commit also includes load and extend operations. Both are
prerequisites for enabling further SIMD spec tests.

Copyright (c) 2020, Arm Limited.
This commit is contained in:
Anton Kirilov
2020-05-28 17:19:36 +01:00
parent fb9f39ce17
commit 51a551fb39
8 changed files with 164 additions and 13 deletions
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5
cranelift/codegen/src/isa/aarch64/lower.rs
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@@ -716,7 +716,8 @@ pub fn ty_bits(ty: Type) -> usize {
B64 | I64 | F64 => 64,
B128 | I128 => 128,
IFLAGS | FFLAGS => 32,
I8X16 | B8X16 => 128,
I8X8 | I16X4 | I32X2 => 64,
B8X16 | I8X16 | I16X8 | I32X4 | I64X2 => 128,
_ => panic!("ty_bits() on unknown type: {:?}", ty),
}
}
@@ -724,7 +725,7 @@ pub fn ty_bits(ty: Type) -> usize {
pub(crate) fn ty_is_int(ty: Type) -> bool {
match ty {
B1 | B8 | I8 | B16 | I16 | B32 | I32 | B64 | I64 => true,
F32 | F64 | B128 | I128 | I8X16 => false,
F32 | F64 | B128 | I128 | I8X8 | I8X16 | I16X4 | I16X8 | I32X2 | I32X4 | I64X2 => false,
IFLAGS | FFLAGS => panic!("Unexpected flags type"),
_ => panic!("ty_is_int() on unknown type: {:?}", ty),
}