From 511c53703ab6f5a7900e2bfbdfb8c7ea26fb47cc Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Tue, 7 Jun 2022 16:56:48 +0100 Subject: [PATCH] cranelift meeting notes for 6-6-22 (#4235) --- meetings/cranelift/2022/cranelift-06-06.md | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/meetings/cranelift/2022/cranelift-06-06.md b/meetings/cranelift/2022/cranelift-06-06.md index 7572245cd5..fd3c3f1a81 100644 --- a/meetings/cranelift/2022/cranelift-06-06.md +++ b/meetings/cranelift/2022/cranelift-06-06.md @@ -17,4 +17,69 @@ ### Attendees +- abrown +- akirilov +- avanhattum +- cfallin +- fitzgen +- sparkerhaynes + ### Notes + +- ISLE porting status and plans? + - abrown: Quarterly goals at Intel, port a number of instructions over to ISLE. + - Want to continue doing so. + - Issue is that all the hard ones are left. + - We need more people to look at it. + - akirilov: Quarterly basis too. + - Our approach was different, we've gone for the harder ones first. + - Trying to improve test coverage. + - abrown: How are you guys tracking coverage? + - akirilov: It's just manual, the bar is currently quite low so easy to see where they're missing. + - Interpreter has failed to handle some cases, something to do with splat. + - Some run tests don't check the return values. + - Sometimes disabling the interpreter tests. + - cfallin: Sounds like the right approach. + - abrown: What's the state of SIMD interpreter support? afonso was working on it. + - cfallin: Don't know what happened to afonso, work has stalled on it. + +- akirilov: Regalloc2 limitation of only 2 reg classes + - SVE will need a predicate file, same for AVX-512. +- cfallin: Bit packing issue, could remove the 'mod' operands and reuse that bit. +- akirilov: Will four classes be enough..? It is probably fine for AArch64. +- cfallin: Will keep this on my back burner. + +# standups + +- fitzgen: No updates. + +- avanhattum: Better semantics for verification. + - SAIL for x64 and arm. + - Figuring out what work is needed to use modern SAIL for x64. + - Working on shim code to avoid annoting machine instructions. + +- akirilov: cranelift CFI patch updates and Fiber changes for MacOS. + - bjorn3 gave feedback and noticed codegen wasn't right. + - some branches were elided and the branch target instructions ended up as the last instruction, not first. + - pointer authentication is still disabled in qemu. + +- cfallin: Implemented alias analysis for load elimination, with okay speedups. + - could have benefitted some option optimizations, such as GVN + - So developing a unified framework for rewrite rules in the mid-end. + - egraphs seem the right approach. + - need an adapter to convert the egraph to LowerCtx: clif -> egraph -> vcode + - Then need to figure out isle rewrite rules. + - Framework will subsume all the existing mid-end optimisations. + - Also worked on a fix regalloc2 issue, reducing stack size usage. + - alexa: static rewrite rules or equality saturation? + - chris: equality. + +- abrown: shared memory in wasmtime. + - impacts cranelift through `memory_size` instruction. + - How are we gonna test this? Looking for ideas and feedback. + - Ported some atomic operations for x64, not sure CAS is right. + +- sparker: Dynamic vector RFC is up in code form. + - It's a bit rough and would greatly appreciate some feedback. + - cfallin: does qemu support sve? + - sparker: yes.