diff --git a/cranelift/src/libcretonne/isa/riscv/mod.rs b/cranelift/src/libcretonne/isa/riscv/mod.rs index 4c24cbb8b7..775154a3d6 100644 --- a/cranelift/src/libcretonne/isa/riscv/mod.rs +++ b/cranelift/src/libcretonne/isa/riscv/mod.rs @@ -1 +1,3 @@ //! RISC-V Instruction Set Architecture. + +pub mod settings; diff --git a/cranelift/src/libcretonne/isa/riscv/settings.rs b/cranelift/src/libcretonne/isa/riscv/settings.rs new file mode 100644 index 0000000000..74d02d5aac --- /dev/null +++ b/cranelift/src/libcretonne/isa/riscv/settings.rs @@ -0,0 +1,5 @@ +//! RISC-V Settings. + +// Include code generated by `meta/gen_settings.py`. This file contains a public `Settings` struct +// with an impl for all of the settings defined in `meta/cretonne/settings.py`. +include!(concat!(env!("OUT_DIR"), "/settings-riscv.rs")); diff --git a/meta/cretonne/__init__.py b/meta/cretonne/__init__.py index 54f20cc678..801ac5a171 100644 --- a/meta/cretonne/__init__.py +++ b/meta/cretonne/__init__.py @@ -875,6 +875,7 @@ class TargetISA(object): def __init__(self, name, instrution_groups): self.name = name + self.settings = None self.instruction_groups = instrution_groups diff --git a/meta/gen_settings.py b/meta/gen_settings.py index accd739cf0..c2545a8c90 100644 --- a/meta/gen_settings.py +++ b/meta/gen_settings.py @@ -99,6 +99,14 @@ def gen_group(sgrp, fmt): def generate(isas, out_dir): + # Generate shared settings. fmt = srcgen.Formatter() gen_group(settings.group, fmt) fmt.update_file('settings.rs', out_dir) + + # Generate ISA-specific settings. + for isa in isas: + if isa.settings: + fmt = srcgen.Formatter() + gen_group(isa.settings, fmt) + fmt.update_file('settings-{}.rs'.format(isa.name), out_dir) diff --git a/meta/isa/riscv/__init__.py b/meta/isa/riscv/__init__.py index 7d51b69b03..ce8c47ea3d 100644 --- a/meta/isa/riscv/__init__.py +++ b/meta/isa/riscv/__init__.py @@ -27,7 +27,7 @@ RV32G / RV64G import defs import encodings +import settings # Re-export the primary target ISA definition. isa = defs.isa - diff --git a/meta/isa/riscv/encodings.py b/meta/isa/riscv/encodings.py index fb6602184c..c148247524 100644 --- a/meta/isa/riscv/encodings.py +++ b/meta/isa/riscv/encodings.py @@ -2,7 +2,6 @@ RISC-V Encodings. """ from cretonne import base -from cretonne.types import i32, i64 from defs import RV32, RV64 from recipes import OP, R diff --git a/meta/isa/riscv/recipes.py b/meta/isa/riscv/recipes.py index ed96836cd4..9719a4b2ec 100644 --- a/meta/isa/riscv/recipes.py +++ b/meta/isa/riscv/recipes.py @@ -18,27 +18,33 @@ from cretonne.formats import Binary # Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ... # The functions below encode the encbits. + def LOAD(funct3): assert funct3 <= 0b111 return 0b00000 | (funct3 << 5) + def STORE(funct3): assert funct3 <= 0b111 return 0b01000 | (funct3 << 5) + def BRANCH(funct3): assert funct3 <= 0b111 return 0b11000 | (funct3 << 5) + def OPIMM(funct3): assert funct3 <= 0b111 return 0b00100 | (funct3 << 5) + def OP(funct3, funct7): assert funct3 <= 0b111 assert funct7 <= 0b1111111 return 0b01100 | (funct3 << 5) | (funct7 << 8) + # R-type 32-bit instructions: These are mostly binary arithmetic instructions. # The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8) R = EncRecipe('R', Binary) diff --git a/meta/isa/riscv/settings.py b/meta/isa/riscv/settings.py new file mode 100644 index 0000000000..d2366ad829 --- /dev/null +++ b/meta/isa/riscv/settings.py @@ -0,0 +1,15 @@ +""" +RISC-V settings. +""" + +from cretonne import SettingGroup, BoolSetting +from defs import isa + +isa.settings = SettingGroup('riscv') + +supports_m = BoolSetting("CPU supports the 'M' extension (mul/div)") +supports_a = BoolSetting("CPU supports the 'A' extension (atomics)") +supports_f = BoolSetting("CPU supports the 'F' extension (float)") +supports_d = BoolSetting("CPU supports the 'D' extension (double)") + +isa.settings.close(globals())