Add RISC-V call instruction encodings.

Calls are jal with a fixed %x1 link register.

lib/cretonne/meta/isa/riscv/encodings.py

@@ -6,7 +6,8 @@ from base import instructions as base
 from base.immediates import intcc
 from .defs import RV32, RV64
 from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
-from .recipes import R, Rshamt, Ricmp, I, Iicmp, Iret, U, UJ, SB, SBzero
+from .recipes import R, Rshamt, Ricmp, I, Iicmp, Iret
+from .recipes import U, UJ, UJcall, SB, SBzero
 from .settings import use_m
 from cdsl.ast import Var
 
@@ -84,6 +85,8 @@ RV64.enc(base.imul.i32, R, OP32(0b000, 0b0000001), isap=use_m)
 # Unconditional branches.
 RV32.enc(base.jump, UJ, JAL())
 RV64.enc(base.jump, UJ, JAL())
+RV32.enc(base.call, UJcall, JAL())
+RV64.enc(base.call, UJcall, JAL())
 
 # Conditional branches.
 for cond,           f3 in [

lib/cretonne/meta/isa/riscv/recipes.py

@@ -12,7 +12,7 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt
 from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
-from base.formats import UnaryImm, BranchIcmp, Branch, Jump
+from base.formats import UnaryImm, BranchIcmp, Branch, Jump, Call
 from .registers import GPR
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
@@ -119,6 +119,7 @@ U = EncRecipe(
 
 # UJ-type unconditional branch instructions.
 UJ = EncRecipe('UJ', Jump, size=4, ins=(), outs=(), branch_range=(0, 21))
+UJcall = EncRecipe('UJcall', Call, size=4, ins=(), outs=())
 
 # SB-type branch instructions.
 # TODO: These instructions have a +/- 4 KB branch range. How to encode that