From 4ebad2060a342ff1a9e8b28bff84225d4c6e1885 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Fri, 19 Aug 2016 14:54:16 -0700
Subject: [PATCH] Add RISC-V encodings for imediate shifts.

Also add the 32-bit shift instructions for RV64.
---
 meta/isa/riscv/encodings.py | 17 ++++++++++++-----
 meta/isa/riscv/recipes.py   | 20 +++++++++++++++++---
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/meta/isa/riscv/encodings.py b/meta/isa/riscv/encodings.py
index c148247524..da5870422f 100644
--- a/meta/isa/riscv/encodings.py
+++ b/meta/isa/riscv/encodings.py
@@ -3,7 +3,7 @@ RISC-V Encodings.
 """
 from cretonne import base
 from defs import RV32, RV64
-from recipes import OP, R
+from recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt
 
 # Basic arithmetic binary instructions are encoded in an R-type instruction.
 for inst,           f3,    f7 in [
@@ -17,12 +17,19 @@ for inst,           f3,    f7 in [
     RV64.enc(inst.i64, R, OP(f3, f7))
 
 # Dynamic shifts have the same masking semantics as the cton base instructions
-for inst,           f3,    f7 in [
-        (base.ishl, 0b001, 0b0000000),
-        (base.ushr, 0b101, 0b0000000),
-        (base.sshr, 0b101, 0b0100000),
+for inst,           inst_imm,      f3,    f7 in [
+        (base.ishl, base.ishl_imm, 0b001, 0b0000000),
+        (base.ushr, base.ushr_imm, 0b101, 0b0000000),
+        (base.sshr, base.sshr_imm, 0b101, 0b0100000),
         ]:
     RV32.enc(inst.i32.i32, R, OP(f3, f7))
     RV64.enc(inst.i64.i64, R, OP(f3, f7))
+    RV64.enc(inst.i32.i32, R, OP32(f3, f7))
     # Allow i32 shift amounts in 64-bit shifts.
     RV64.enc(inst.i64.i32, R, OP(f3, f7))
+    RV64.enc(inst.i32.i64, R, OP32(f3, f7))
+
+    # Immediate shifts.
+    RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
+    RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
+    RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
diff --git a/meta/isa/riscv/recipes.py b/meta/isa/riscv/recipes.py
index 9719a4b2ec..49352b817a 100644
--- a/meta/isa/riscv/recipes.py
+++ b/meta/isa/riscv/recipes.py
@@ -9,7 +9,7 @@ instruction formats described in the reference:
     Version 2.1
 """
 from cretonne import EncRecipe
-from cretonne.formats import Binary
+from cretonne.formats import Binary, BinaryImm
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
 # instructions have 11 as the two low bits, with bits 6:2 determining the base
@@ -34,9 +34,14 @@ def BRANCH(funct3):
     return 0b11000 | (funct3 << 5)
 
 
-def OPIMM(funct3):
+def OPIMM(funct3, funct7=0):
     assert funct3 <= 0b111
-    return 0b00100 | (funct3 << 5)
+    return 0b00100 | (funct3 << 5) | (funct7 << 8)
+
+
+def OPIMM32(funct3, funct7=0):
+    assert funct3 <= 0b111
+    return 0b00110 | (funct3 << 5) | (funct7 << 8)
 
 
 def OP(funct3, funct7):
@@ -45,6 +50,15 @@ def OP(funct3, funct7):
     return 0b01100 | (funct3 << 5) | (funct7 << 8)
 
 
+def OP32(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01110 | (funct3 << 5) | (funct7 << 8)
+
+
 # R-type 32-bit instructions: These are mostly binary arithmetic instructions.
 # The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
 R = EncRecipe('R', Binary)
+
+# R-type with an immediate shift amount instead of rs2.
+Rshamt = EncRecipe('Rshamt', BinaryImm)