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Codegen fix fcvt_from_sint.f32 with small types on riscv64. (#5964)

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* fix issue5952

* We should only extend i8 and i16

* remove extra space

* move some code
This commit is contained in:
yuyang
2023-03-10 18:29:55 +08:00
committed by GitHub
parent 0ec7b872fa
commit 4e875f33a7
4 changed files with 42 additions and 10 deletions
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28
cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
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@@ -10,12 +10,14 @@ block0(v0: i8):
; VCode:
; block0:
; fcvt.s.lu fa0,a0
; andi t2,a0,255
; fcvt.s.lu fa0,t2
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.s.lu fa0, a0
; andi t2, a0, 0xff
; fcvt.s.lu fa0, t2
; ret
function u0:0(i8) -> f64 {
@@ -26,12 +28,14 @@ block0(v0: i8):
; VCode:
; block0:
; fcvt.d.lu fa0,a0
; andi t2,a0,255
; fcvt.d.lu fa0,t2
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.d.lu fa0, a0
; andi t2, a0, 0xff
; fcvt.d.lu fa0, t2
; ret
function u0:0(i16) -> f32 {
@@ -42,12 +46,16 @@ block0(v0: i16):
; VCode:
; block0:
; fcvt.s.lu fa0,a0
; slli t2,a0,48
; srli a1,t2,48
; fcvt.s.lu fa0,a1
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.s.lu fa0, a0
; slli t2, a0, 0x30
; srli a1, t2, 0x30
; fcvt.s.lu fa0, a1
; ret
function u0:0(i16) -> f64 {
@@ -58,12 +66,16 @@ block0(v0: i16):
; VCode:
; block0:
; fcvt.d.lu fa0,a0
; slli t2,a0,48
; srli a1,t2,48
; fcvt.d.lu fa0,a1
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.d.lu fa0, a0
; slli t2, a0, 0x30
; srli a1, t2, 0x30
; fcvt.d.lu fa0, a1
; ret
function u0:0(f32) -> i8 {