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Codegen fix fcvt_from_sint.f32 with small types on riscv64. (#5964)

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* fix issue5952

* We should only extend i8 and i16

* remove extra space

* move some code
This commit is contained in:
yuyang
2023-03-10 18:29:55 +08:00
committed by GitHub
parent 0ec7b872fa
commit 4e875f33a7
4 changed files with 42 additions and 10 deletions
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6
cranelift/codegen/src/isa/riscv64/inst.isle
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@@ -1925,6 +1925,12 @@
(rule (normalize_cmp_value $I64 r _) r)
(rule (normalize_cmp_value $I128 r _) r)
(decl normalize_fcvt_from_int (ValueRegs Type ExtendOp) ValueRegs)
(rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op)
(extend r op ty $I64))
(rule 1 (normalize_fcvt_from_int r _ _)
r)
;; Convert a truthy value, possibly of more than one register (an
;; I128), to one register. If narrower than 64 bits, must have already
;; been masked (e.g. by `normalize_cmp_value`).

4
cranelift/codegen/src/isa/riscv64/lower.isle
View File

@@ -802,12 +802,12 @@
;;;;; Rules for `fcvt_from_sint`;;;;;;;;;
(rule
(lower (has_type to (fcvt_from_sint v @ (value_type from))))
(fpu_rr (int_convert_2_float_op from $true to) to v))
(fpu_rr (int_convert_2_float_op from $true to) to (normalize_fcvt_from_int v from (ExtendOp.Signed))))
;;;;; Rules for `fcvt_from_uint`;;;;;;;;;
(rule
(lower (has_type to (fcvt_from_uint v @ (value_type from))))
(fpu_rr (int_convert_2_float_op from $false to) to v))
(fpu_rr (int_convert_2_float_op from $false to) to (normalize_fcvt_from_int v from (ExtendOp.Zero))))
;;;;; Rules for `symbol_value`;;;;;;;;;
(rule