Use the target-lexicon crate.

This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
2018-05-25 11:41:14 -07:00
parent 2f3008aa40
commit 4e67e08efd
131 changed files with 487 additions and 499 deletions
--- a/cranelift/filetests/regalloc/aliases.cton
+++ b/cranelift/filetests/regalloc/aliases.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 function %value_aliases(i32, f32, i64 vmctx) baldrdash {
    gv0 = vmctx
--- a/cranelift/filetests/regalloc/basic.cton
+++ b/cranelift/filetests/regalloc/basic.cton
@@ -1,7 +1,7 @@
 test regalloc

 ; We can add more ISAs once they have defined encodings.
-isa riscv
+target riscv32

 ; regex: RX=%x\d+

--- a/cranelift/filetests/regalloc/coalesce.cton
+++ b/cranelift/filetests/regalloc/coalesce.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa riscv
+target riscv32

 ; Test the coalescer.
 ; regex: V=v\d+
--- a/cranelift/filetests/regalloc/coalescing-207.cton
+++ b/cranelift/filetests/regalloc/coalescing-207.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 ; Reported as https://github.com/cretonne/cretonne/issues/207
 ;
--- a/cranelift/filetests/regalloc/coalescing-216.cton
+++ b/cranelift/filetests/regalloc/coalescing-216.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 ; Reported as https://github.com/cretonne/cretonne/issues/216 from the Binaryen fuzzer.
 ;
--- a/cranelift/filetests/regalloc/coloring-227.cton
+++ b/cranelift/filetests/regalloc/coloring-227.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
    gv0 = vmctx
--- a/cranelift/filetests/regalloc/constraints.cton
+++ b/cranelift/filetests/regalloc/constraints.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa x86
+target i686

 ; regex: V=v\d+
 ; regex: REG=%r([abcd]x|[sd]i)
--- a/cranelift/filetests/regalloc/ghost-param.cton
+++ b/cranelift/filetests/regalloc/ghost-param.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 ; This test case would create an EBB parameter that was a ghost value.
 ; The coalescer would insert a copy of the ghost value, leading to verifier errors.
--- a/cranelift/filetests/regalloc/global-constraints.cton
+++ b/cranelift/filetests/regalloc/global-constraints.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa x86
+target i686

 ; This test covers the troubles when values with global live ranges are defined
 ; by instructions with constrained register classes.
--- a/cranelift/filetests/regalloc/global-fixed.cton
+++ b/cranelift/filetests/regalloc/global-fixed.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell

 function %foo() system_v {
 ebb4:
--- a/cranelift/filetests/regalloc/infinite-interference.cton
+++ b/cranelift/filetests/regalloc/infinite-interference.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa riscv
+target riscv32

 ; Here, the coalescer initially builds vreg0 = [v1, v2, v3]
 ;
--- a/cranelift/filetests/regalloc/iterate.cton
+++ b/cranelift/filetests/regalloc/iterate.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] baldrdash {
 ebb0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):
--- a/cranelift/filetests/regalloc/multi-constraints.cton
+++ b/cranelift/filetests/regalloc/multi-constraints.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 ; Test combinations of constraints.
 ;
--- a/cranelift/filetests/regalloc/output-interference.cton
+++ b/cranelift/filetests/regalloc/output-interference.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell

 function %test(i64) -> i64 system_v {
 ebb0(v0: i64):
--- a/cranelift/filetests/regalloc/reload-208.cton
+++ b/cranelift/filetests/regalloc/reload-208.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell

 ; regex: V=v\d+

--- a/cranelift/filetests/regalloc/reload.cton
+++ b/cranelift/filetests/regalloc/reload.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa riscv enable_e
+target riscv32 enable_e

 ; regex: V=v\d+

--- a/cranelift/filetests/regalloc/schedule-moves.cton
+++ b/cranelift/filetests/regalloc/schedule-moves.cton
@@ -1,5 +1,5 @@
 test regalloc
-isa x86 haswell
+target i686 haswell

 function %pr165() system_v {
 ebb0:
--- a/cranelift/filetests/regalloc/spill-noregs.cton
+++ b/cranelift/filetests/regalloc/spill-noregs.cton
@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86
+target x86_64

 ; Test case found by the Binaryen fuzzer.
 ;
--- a/cranelift/filetests/regalloc/spill.cton
+++ b/cranelift/filetests/regalloc/spill.cton
@@ -12,7 +12,7 @@ test regalloc
 ; regex: V=v\d+
 ; regex: WS=\s+

-isa riscv enable_e
+target riscv32 enable_e

 ; In straight-line code, the first value defined is spilled.
 ; That is in order:
--- a/cranelift/filetests/regalloc/unreachable_code.cton
+++ b/cranelift/filetests/regalloc/unreachable_code.cton
@@ -1,9 +1,8 @@
 ; Use "test compile" here otherwise the dead blocks won't be eliminated.
 test compile

-set is_64bit
 set probestack_enabled=0
-isa x86 haswell
+target x86_64 haswell

 ; This function contains unreachable blocks which trip up the register
 ; allocator if they don't get cleared out.
--- a/cranelift/filetests/regalloc/x86-regres.cton
+++ b/cranelift/filetests/regalloc/x86-regres.cton
@@ -1,6 +1,6 @@
 test regalloc

-isa x86
+target i686

 ; regex: V=v\d+