Use the target-lexicon crate.

This switches from a custom list of architectures to use the
target-lexicon crate.

 - "set is_64bit=1; isa x86" is replaced with "target x86_64", and
   similar for other architectures, and the `is_64bit` flag is removed
   entirely.

 - The `is_compressed` flag is removed too; it's no longer being used to
   control REX prefixes on x86-64, ARM and Thumb are separate
   architectures in target-lexicon, and we can figure out how to
   select RISC-V compressed encodings when we're ready.

cranelift/filetests/isa/riscv/abi-e.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures for RV32E.
 test legalizer
-isa riscv enable_e
+target riscv32 enable_e
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/abi.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/binary32.cton

@@ -1,6 +1,6 @@
 ; Binary emission of 32-bit code.
 test binemit
-isa riscv
+target riscv32
 
 function %RV32I(i32 link [%x1]) -> i32 link [%x1] {
     sig0 = ()

cranelift/filetests/isa/riscv/encoding.cton

@@ -1,5 +1,5 @@
 test legalizer
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
 function %int32(i32, i32) {
 ebb0(v1: i32, v2: i32):

cranelift/filetests/isa/riscv/expand-i32.cton

@@ -1,11 +1,9 @@
 ; Test the legalization of i32 instructions that don't have RISC-V versions.
 test legalizer
 
-set is_64bit=0
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
-set is_64bit=1
-isa riscv supports_m=1
+target riscv64 supports_m=1
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/legalize-abi.cton

@@ -1,6 +1,6 @@
 ; Test legalizer's handling of ABI boundaries.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 ; regex: SS=ss\d+

cranelift/filetests/isa/riscv/legalize-i64.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of i64 arithmetic instructions.
 test legalizer
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/parse-encoding.cton

@@ -1,6 +1,6 @@
 ; Test the parser's support for encoding annotations.
 test legalizer
-isa riscv
+target riscv32
 
 function %parse_encoding(i32 [%x5]) -> i32 [%x10] {
     ; check: function %parse_encoding(i32 [%x5], i32 link [%x1]) -> i32 [%x10], i32 link [%x1] fast {

cranelift/filetests/isa/riscv/regmove.cton

@@ -1,6 +1,6 @@
 ; Test tracking of register moves.
 test binemit
-isa riscv
+target riscv32
 
 function %regmoves(i32 link [%x1]) -> i32 link [%x1] {
 ebb0(v9999: i32):

cranelift/filetests/isa/riscv/split-args.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of EBB arguments that are split.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/verify-encoding.cton

@@ -1,5 +1,5 @@
 test verifier
-isa riscv
+target riscv32
 
 function %RV32I(i32 link [%x1]) -> i32 link [%x1] {
     fn0 = %foo()