Add icmp_imm encodings for RISC-V.

The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.

lib/cretonne/meta/isa/riscv/recipes.py

@@ -11,7 +11,7 @@ instruction formats described in the reference:
 from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt
-from base.formats import Binary, BinaryImm, MultiAry, IntCompare
+from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
 from .registers import GPR
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
@@ -86,6 +86,11 @@ I = EncRecipe(
         'I', BinaryImm, ins=GPR, outs=GPR,
         instp=IsSignedInt(BinaryImm.imm, 12))
 
+# I-type encoding of an integer comparison.
+Iicmp = EncRecipe(
+        'Iicmp', IntCompareImm, ins=GPR, outs=GPR,
+        instp=IsSignedInt(IntCompareImm.imm, 12))
+
 # I-type encoding for `jalr` as a return instruction. We won't use the
 # immediate offset.
 # The variable return values are not encoded.