Add x86 SIMD band

cranelift/codegen/meta/src/isa/x86/encodings.rs

@@ -1973,8 +1973,13 @@ pub(crate) fn define<'defs>(
         e.enc_32_64_maybe_isap(imul, rec_fa.opcodes(opcodes), *isap);
     }
 
-    // SIMD bor
+    // SIMD logical operations
     for ty in ValueType::all_lane_types().filter(allowed_simd_type) {
+        // band
+        let band = band.bind(vector(ty, sse_vector_size));
+        e.enc_32_64(band, rec_fa.opcodes(&PAND));
+
+        // bor
         let bor = bor.bind(vector(ty, sse_vector_size));
         e.enc_32_64(bor, rec_fa.nonrex().opcodes(&POR));
     }

cranelift/codegen/meta/src/isa/x86/opcodes.rs

@@ -263,6 +263,9 @@ pub static PADDUSB: [u8; 3] = [0x66, 0x0f, 0xdc];
 /// Add packed unsigned word integers from xmm2/m128 and xmm1 saturate the results (SSE).
 pub static PADDUSW: [u8; 3] = [0x66, 0x0f, 0xdd];
 
+/// Bitwise AND of xmm2/m128 and xmm1 (SSE2).
+pub static PAND: [u8; 3] = [0x66, 0x0f, 0xdb];
+
 /// Compare packed data for equal (SSE2).
 pub static PCMPEQB: [u8; 3] = [0x66, 0x0f, 0x74];
 

cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif

@@ -0,0 +1,15 @@
+test binemit
+set enable_simd
+target x86_64 skylake
+
+function %bor_b16x8(b16x8, b16x8) -> b16x8 {
+ebb0(v0: b16x8 [%xmm2], v1: b16x8 [%xmm1]):
+[-, %xmm2]  v2 = bor v0, v1     ; bin: 66 0f eb d1
+            return v2
+}
+
+function %band_b64x2(b64x2, b64x2) -> b64x2 {
+ebb0(v0: b64x2 [%xmm6], v1: b64x2 [%xmm3]):
+[-, %xmm6]  v2 = band v0, v1      ; bin: 66 0f db f3
+            return v2
+}