cranelift: Add Bswap instruction (#1092) (#5147)

Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

Updated x64 RexFlags type to support emitting for single-operand
instructions like bswap

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap was already supported in backend, just had to add
a bit of plumbing

* For completeness, added bswap to the interpreter as well.

* added filetests and runtests for each ISA

* added bswap to fuzzgen, thanks to afonso360 for the code there

* 128-bit swaps are not yet implemented, that can be done later

cranelift/fuzzgen/src/function_generator.rs

@@ -671,6 +671,13 @@ const OPCODE_SIGNATURES: &'static [(
     (Opcode::Bmask, &[I32], &[I128], insert_opcode),
     (Opcode::Bmask, &[I64], &[I128], insert_opcode),
     (Opcode::Bmask, &[I128], &[I128], insert_opcode),
+    // Bswap
+    (Opcode::Bswap, &[I16, I16], &[I16], insert_opcode),
+    (Opcode::Bswap, &[I32, I32], &[I32], insert_opcode),
+    (Opcode::Bswap, &[I64, I64], &[I64], insert_opcode),
+    // I128 version not yet implemented.
+    #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
+    (Opcode::Bswap, &[I128, I128], &[I128], insert_opcode),
     // Fadd
     (Opcode::Fadd, &[F32, F32], &[F32], insert_opcode),
     (Opcode::Fadd, &[F64, F64], &[F64], insert_opcode),