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riscv64: Delete SelectIf instruction (#5888)

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* riscv64: Delete `SelectIf` instruction

* riscv64: Fix typo in comment

Co-authored-by: Trevor Elliott <awesomelyawesome@gmail.com>

* riscv64: Improve `bmask` codegen

* riscv64: Use `lower_bmask` in `select_spectre_guard`

* riscv64: Use `lower_bmask` to extend values in `select_spectre_guard`

Co-authored-by: Trevor Elliott <awesomelyawesome@gmail.com>

---------

Co-authored-by: Trevor Elliott <awesomelyawesome@gmail.com>
This commit is contained in:
Afonso Bordado
2023-04-11 18:33:32 +01:00
committed by GitHub
parent 9acb649f17
commit 4c32dd7786
43 changed files with 2366 additions and 924 deletions
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42
cranelift/codegen/src/isa/riscv64/inst/emit.rs
View File

@@ -1864,48 +1864,6 @@ impl MachInstEmit for Inst {
}
sink.put_data(Inst::TRAP_OPCODE);
}
&Inst::SelectIf {
if_spectre_guard: _if_spectre_guard, // _if_spectre_guard not use because it is used to not be removed by optimization pass and some other staff.
ref rd,
test,
ref x,
ref y,
} => {
let label_select_x = sink.get_label();
let label_select_y = sink.get_label();
let label_jump_over = sink.get_label();
let test = allocs.next(test);
let x = alloc_value_regs(x, &mut allocs);
let y = alloc_value_regs(y, &mut allocs);
let rd: Vec<_> = rd.iter().map(|r| allocs.next_writable(*r)).collect();
Inst::CondBr {
taken: BranchTarget::Label(label_select_x),
not_taken: BranchTarget::Label(label_select_y),
kind: IntegerCompare {
kind: IntCC::NotEqual,
rs1: test,
rs2: zero_reg(),
},
}
.emit(&[], sink, emit_info, state);
// here select x.
sink.bind_label(label_select_x, &mut state.ctrl_plane);
gen_moves(&rd[..], x.regs())
.into_iter()
.for_each(|i| i.emit(&[], sink, emit_info, state));
// jump over
Inst::Jal {
dest: BranchTarget::Label(label_jump_over),
}
.emit(&[], sink, emit_info, state);
// here select y.
sink.bind_label(label_select_y, &mut state.ctrl_plane);
gen_moves(&rd[..], y.regs())
.into_iter()
.for_each(|i| i.emit(&[], sink, emit_info, state));
sink.bind_label(label_jump_over, &mut state.ctrl_plane);
}
&Inst::AtomicLoad { rd, ty, p } => {
let p = allocs.next(p);
let rd = allocs.next_writable(rd);

37
cranelift/codegen/src/isa/riscv64/inst/mod.rs
View File

@@ -526,18 +526,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_early_def(tmp);
collector.reg_early_def(rd);
}
&Inst::SelectIf {
ref rd,
test,
ref x,
ref y,
..
} => {
collector.reg_use(test);
collector.reg_uses(x.regs());
collector.reg_uses(y.regs());
rd.iter().for_each(|r| collector.reg_early_def(*r));
}
&Inst::RawData { .. } => {}
&Inst::AtomicStore { src, p, .. } => {
collector.reg_use(src);
@@ -1012,31 +1000,6 @@ impl Inst {
rd, rs, tmp, tmp2, step, ty
)
}
&Inst::SelectIf {
if_spectre_guard,
ref rd,
test,
ref x,
ref y,
} => {
let test = format_reg(test, allocs);
let x = format_regs(x.regs(), allocs);
let y = format_regs(y.regs(), allocs);
let rd: Vec<_> = rd.iter().map(|r| r.to_reg()).collect();
let rd = format_regs(&rd[..], allocs);
format!(
"selectif{} {},{},{}##test={}",
if if_spectre_guard {
"_spectre_guard"
} else {
""
},
rd,
x,
y,
test
)
}
&Inst::Popcnt {
sum,
step,