Merge pull request #1999 from bnjbvr/fix-aarch64-ishl-by-zero

machinst aarch64: fix encoding generation of left-shift by 0
2020-07-13 09:25:21 -07:00
parent f4f5eed254 f316bef763
commit 4b6ebc0c27
2 changed files with 30 additions and 2 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -934,6 +934,26 @@ fn test_aarch64_binemit() {
        "280141D3",
        "lsl x8, x9, #63",
    ));
+    insns.push((
+        Inst::AluRRImmShift {
+            alu_op: ALUOp::Lsl32,
+            rd: writable_xreg(10),
+            rn: xreg(11),
+            immshift: ImmShift::maybe_from_u64(0).unwrap(),
+        },
+        "6A7D0053",
+        "lsl w10, w11, #0",
+    ));
+    insns.push((
+        Inst::AluRRImmShift {
+            alu_op: ALUOp::Lsl64,
+            rd: writable_xreg(10),
+            rn: xreg(11),
+            immshift: ImmShift::maybe_from_u64(0).unwrap(),
+        },
+        "6AFD40D3",
+        "lsl x10, x11, #0",
+    ));

    insns.push((
        Inst::AluRRImmLogic {