cranelift-codegen: move old x86 and RISC-V backends to isa/legacy/.
These backends will be removed in the future (see bytecodealliance/rfcs#12 and the pending #3009 in this repo). In the meantime, to more clearly communicate that they are using "legacy" APIs and will eventually be removed, this PR places them in an `isa/legacy/` subdirectory. No functional changes otherwise.
This commit is contained in:
Chris Fallin
265
cranelift/codegen/src/isa/legacy/x86/unwind/winx64.rs
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265
cranelift/codegen/src/isa/legacy/x86/unwind/winx64.rs
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//! Unwind information for Windows x64 ABI.
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use crate::ir::Function;
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use crate::isa::x86::registers::{FPR, GPR};
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use crate::isa::{unwind::winx64::UnwindInfo, RegUnit, TargetIsa};
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use crate::result::CodegenResult;
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pub(crate) fn create_unwind_info(
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func: &Function,
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isa: &dyn TargetIsa,
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) -> CodegenResult<Option<UnwindInfo>> {
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// Only Windows fastcall is supported for unwind information
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if !func.signature.call_conv.extends_windows_fastcall() || func.prologue_end.is_none() {
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return Ok(None);
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}
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let unwind = match super::create_unwind_info(func, isa)? {
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Some(u) => u,
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None => {
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return Ok(None);
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}
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};
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Ok(Some(UnwindInfo::build::<RegUnit, RegisterMapper>(unwind)?))
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}
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struct RegisterMapper;
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impl crate::isa::unwind::winx64::RegisterMapper<RegUnit> for RegisterMapper {
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fn map(reg: RegUnit) -> crate::isa::unwind::winx64::MappedRegister {
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use crate::isa::unwind::winx64::MappedRegister;
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if GPR.contains(reg) {
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MappedRegister::Int(GPR.index_of(reg) as u8)
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} else if FPR.contains(reg) {
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MappedRegister::Xmm(reg as u8)
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} else {
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panic!()
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}
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::cursor::{Cursor, FuncCursor};
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use crate::ir::{ExternalName, InstBuilder, Signature, StackSlotData, StackSlotKind};
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use crate::isa::unwind::winx64::UnwindCode;
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use crate::isa::x86::registers::RU;
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use crate::isa::{lookup_variant, BackendVariant, CallConv};
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use crate::settings::{builder, Flags};
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use crate::Context;
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use std::str::FromStr;
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use target_lexicon::triple;
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#[test]
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fn test_wrong_calling_convention() {
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let isa = lookup_variant(triple!("x86_64"), BackendVariant::Legacy)
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_function(CallConv::SystemV, None));
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context.compile(&*isa).expect("expected compilation");
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assert_eq!(
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create_unwind_info(&context.func, &*isa).expect("can create unwind info"),
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None
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);
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}
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#[test]
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fn test_small_alloc() {
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let isa = lookup_variant(triple!("x86_64"), BackendVariant::Legacy)
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_function(
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CallConv::WindowsFastcall,
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Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
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));
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context.compile(&*isa).expect("expected compilation");
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let unwind = create_unwind_info(&context.func, &*isa)
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.expect("can create unwind info")
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.expect("expected unwind info");
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assert_eq!(
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unwind,
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UnwindInfo {
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flags: 0,
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prologue_size: 9,
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frame_register: None,
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frame_register_offset: 0,
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unwind_codes: vec![
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UnwindCode::PushRegister {
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instruction_offset: 2,
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reg: GPR.index_of(RU::rbp.into()) as u8
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},
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UnwindCode::StackAlloc {
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instruction_offset: 9,
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size: 64
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}
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]
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}
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);
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assert_eq!(unwind.emit_size(), 8);
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let mut buf = [0u8; 8];
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unwind.emit(&mut buf);
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assert_eq!(
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buf,
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[
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0x01, // Version and flags (version 1, no flags)
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0x09, // Prologue size
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0x02, // Unwind code count (1 for stack alloc, 1 for push reg)
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0x00, // Frame register + offset (no frame register)
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0x09, // Prolog offset
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0x72, // Operation 2 (small stack alloc), size = 0xB slots (e.g. (0x7 * 8) + 8 = 64 bytes)
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0x02, // Prolog offset
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0x50, // Operation 0 (save nonvolatile register), reg = 5 (RBP)
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]
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);
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}
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#[test]
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fn test_medium_alloc() {
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let isa = lookup_variant(triple!("x86_64"), BackendVariant::Legacy)
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_function(
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CallConv::WindowsFastcall,
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Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 10000)),
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));
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context.compile(&*isa).expect("expected compilation");
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let unwind = create_unwind_info(&context.func, &*isa)
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.expect("can create unwind info")
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.expect("expected unwind info");
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assert_eq!(
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unwind,
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UnwindInfo {
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flags: 0,
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prologue_size: 27,
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frame_register: None,
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frame_register_offset: 0,
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unwind_codes: vec![
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UnwindCode::PushRegister {
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instruction_offset: 2,
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reg: GPR.index_of(RU::rbp.into()) as u8
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},
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UnwindCode::StackAlloc {
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instruction_offset: 27,
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size: 10000
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}
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]
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}
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);
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assert_eq!(unwind.emit_size(), 12);
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let mut buf = [0u8; 12];
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unwind.emit(&mut buf);
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assert_eq!(
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buf,
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[
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0x01, // Version and flags (version 1, no flags)
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0x1B, // Prologue size
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0x03, // Unwind code count (2 for stack alloc, 1 for push reg)
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0x00, // Frame register + offset (no frame register)
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0x1B, // Prolog offset
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0x01, // Operation 1 (large stack alloc), size is scaled 16-bits (info = 0)
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0xE2, // Low size byte
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0x04, // High size byte (e.g. 0x04E2 * 8 = 10000 bytes)
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0x02, // Prolog offset
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0x50, // Operation 0 (push nonvolatile register), reg = 5 (RBP)
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0x00, // Padding
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0x00, // Padding
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]
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);
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}
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#[test]
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fn test_large_alloc() {
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let isa = lookup_variant(triple!("x86_64"), BackendVariant::Legacy)
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_function(
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CallConv::WindowsFastcall,
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Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 1000000)),
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));
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context.compile(&*isa).expect("expected compilation");
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let unwind = create_unwind_info(&context.func, &*isa)
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.expect("can create unwind info")
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.expect("expected unwind info");
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assert_eq!(
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unwind,
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UnwindInfo {
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flags: 0,
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prologue_size: 27,
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frame_register: None,
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frame_register_offset: 0,
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unwind_codes: vec![
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UnwindCode::PushRegister {
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instruction_offset: 2,
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reg: GPR.index_of(RU::rbp.into()) as u8
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},
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UnwindCode::StackAlloc {
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instruction_offset: 27,
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size: 1000000
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}
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]
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}
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);
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assert_eq!(unwind.emit_size(), 12);
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let mut buf = [0u8; 12];
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unwind.emit(&mut buf);
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assert_eq!(
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buf,
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[
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0x01, // Version and flags (version 1, no flags)
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0x1B, // Prologue size
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0x04, // Unwind code count (3 for stack alloc, 1 for push reg)
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0x00, // Frame register + offset (no frame register)
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0x1B, // Prolog offset
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0x11, // Operation 1 (large stack alloc), size is unscaled 32-bits (info = 1)
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0x40, // Byte 1 of size
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0x42, // Byte 2 of size
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0x0F, // Byte 3 of size
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0x00, // Byte 4 of size (size is 0xF4240 = 1000000 bytes)
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0x02, // Prolog offset
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0x50, // Operation 0 (push nonvolatile register), reg = 5 (RBP)
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]
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);
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}
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fn create_function(call_conv: CallConv, stack_slot: Option<StackSlotData>) -> Function {
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let mut func =
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Function::with_name_signature(ExternalName::user(0, 0), Signature::new(call_conv));
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let block0 = func.dfg.make_block();
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let mut pos = FuncCursor::new(&mut func);
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pos.insert_block(block0);
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pos.ins().return_(&[]);
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if let Some(stack_slot) = stack_slot {
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func.stack_slots.push(stack_slot);
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}
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func
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}
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}
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