diff --git a/lib/cretonne/src/regalloc/allocatable_set.rs b/lib/cretonne/src/regalloc/allocatable_set.rs
index c6f8c86a07..355443affc 100644
--- a/lib/cretonne/src/regalloc/allocatable_set.rs
+++ b/lib/cretonne/src/regalloc/allocatable_set.rs
@@ -6,6 +6,7 @@
 //! share a register unit can't be in use at the same time.
 
 use isa::registers::{RegInfo, RegUnit, RegUnitMask, RegClass};
+use std::char;
 use std::fmt;
 use std::iter::ExactSizeIterator;
 use std::mem::size_of_val;
@@ -51,14 +52,26 @@ impl AllocatableSet {
     /// It is an error to take a register that doesn't have all of its register units available.
     pub fn take(&mut self, rc: RegClass, reg: RegUnit) {
         let (idx, bits) = bitmask(rc, reg);
-        debug_assert_eq!(self.avail[idx] & bits, bits, "Not available");
+        debug_assert!(
+            (self.avail[idx] & bits) == bits,
+            "{}:{} not available in {}",
+            rc,
+            rc.info.display_regunit(reg),
+            self.display(rc.info)
+        );
         self.avail[idx] &= !bits;
     }
 
     /// Make `reg` available for allocation again.
     pub fn free(&mut self, rc: RegClass, reg: RegUnit) {
         let (idx, bits) = bitmask(rc, reg);
-        debug_assert_eq!(self.avail[idx] & bits, 0, "Not allocated");
+        debug_assert!(
+            (self.avail[idx] & bits) == 0,
+            "{}:{} not allocated in {}",
+            rc,
+            rc.info.display_regunit(reg),
+            self.display(rc.info)
+        );
         self.avail[idx] |= bits;
     }
 
@@ -165,9 +178,28 @@ impl<'a> fmt::Display for DisplayAllocatableSet<'a> {
                     .expect("No register banks");
                 for rc in &reginfo.classes[0..toprcs] {
                     if rc.width == 1 {
-                        write!(f, " {}:", rc)?;
-                        for u in self.0.iter(rc) {
-                            write!(f, " {}", reginfo.display_regunit(u))?;
+                        let bank = &reginfo.banks[rc.bank as usize];
+                        write!(f, " {}: ", rc)?;
+                        for offset in 0..bank.units {
+                            let reg = bank.first_unit + offset;
+                            if !rc.contains(reg) {
+                                continue;
+                            }
+                            if !self.0.is_avail(rc, reg) {
+                                write!(f, "-")?;
+                                continue;
+                            }
+                            // Display individual registers as either the second letter of their
+                            // name or the last digit of their number.
+                            // This works for Intel (rax, rbx, ...) and for numbered regs.
+                            write!(
+                                f,
+                                "{}",
+                                bank.names
+                                    .get(offset as usize)
+                                    .and_then(|name| name.chars().skip(1).next())
+                                    .unwrap_or(char::from_digit((offset % 10) as u32, 10).unwrap())
+                            )?;
                         }
                     }
                 }
diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index d5d7e804f7..8c4de9163f 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -287,7 +287,7 @@ impl<'a> Context<'a> {
         regs: &mut AllocatableSet,
     ) {
         dbg!(
-            "Coloring {}\n          {}",
+            "Coloring {}\n    from {}",
             self.cur.display_inst(inst),
             regs.display(&self.reginfo)
         );
diff --git a/lib/cretonne/src/regalloc/solver.rs b/lib/cretonne/src/regalloc/solver.rs
index ae5f23afb4..f21993a4c7 100644
--- a/lib/cretonne/src/regalloc/solver.rs
+++ b/lib/cretonne/src/regalloc/solver.rs
@@ -962,7 +962,10 @@ impl Solver {
 
 impl fmt::Display for Solver {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        let reginfo = self.vars.first().map(|v| v.constraint.info);
         writeln!(f, "Solver {{ inputs_done: {},", self.inputs_done)?;
+        writeln!(f, "  in:  {}", self.regs_in.display(reginfo))?;
+        writeln!(f, "  out: {}", self.regs_out.display(reginfo))?;
         writeln!(
             f,
             "  assignments: {}",