[codegen] Make scalar_to_vector's output type a lane of its input type;

cranelift/codegen/meta/src/isa/x86/encodings.rs

@@ -1729,9 +1729,7 @@ pub fn define(
     // to the Intel manual: "When the destination operand is an XMM register, the source operand is
     // written to the low doubleword of the register and the regiser is zero-extended to 128 bits."
     for ty in ValueType::all_lane_types().filter(|t| t.lane_bits() >= 8) {
-        let instruction = scalar_to_vector
+        let instruction = scalar_to_vector.bind_vector_from_lane(ty, sse_vector_size);
-            .bind_vector_from_lane(ty, sse_vector_size)
-            .bind(ty);
         let template = rec_frurm.opcodes(vec![0x66, 0x0f, 0x6e]); // MOVD/MOVQ
         if ty.lane_bits() < 64 {
             // no 32-bit encodings for 64-bit widths

cranelift/codegen/meta/src/shared/instructions.rs

@@ -113,16 +113,6 @@ pub fn define(
             .build(),
     );
 
-    let Scalar = &TypeVar::new(
-        "scalar",
-        "Any scalar value that can be used as a lane in a vector",
-        TypeSetBuilder::new()
-            .bools(Interval::All)
-            .ints(Interval::All)
-            .floats(Interval::All)
-            .build(),
-    );
-
     let Any = &TypeVar::new(
         "Any",
         "Any integer, float, boolean, or reference scalar or vector type",
@@ -2772,8 +2762,8 @@ pub fn define(
         .operands_out(vec![a]),
     );
 
-    let s = &operand_doc("s", Scalar, "A scalar value");
+    let a = &operand_doc("a", TxN, "A vector value");
-    let a = &operand_doc("a", TxN, "A vector value (i.e. held in an XMM register)");
+    let s = &operand_doc("s", &TxN.lane_of(), "A scalar value");
 
     ig.push(
         Inst::new(

cranelift/filetests/filetests/verifier/scalar-to-vector.clif

@@ -0,0 +1,10 @@
+test verifier
+set enable_simd=true
+target x86_64
+
+function %scalar_to_vector() {
+ebb0:
+    v0 = iconst.i32 42
+    v1 = scalar_to_vector.f32x4 v0 ; error: arg 0 (v0) has type i32, expected f32
+    return
+}