[codegen] Make scalar_to_vector's output type a lane of its input type;
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@@ -1729,9 +1729,7 @@ pub fn define(
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// to the Intel manual: "When the destination operand is an XMM register, the source operand is
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// written to the low doubleword of the register and the regiser is zero-extended to 128 bits."
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for ty in ValueType::all_lane_types().filter(|t| t.lane_bits() >= 8) {
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let instruction = scalar_to_vector
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.bind_vector_from_lane(ty, sse_vector_size)
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.bind(ty);
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let instruction = scalar_to_vector.bind_vector_from_lane(ty, sse_vector_size);
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let template = rec_frurm.opcodes(vec![0x66, 0x0f, 0x6e]); // MOVD/MOVQ
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if ty.lane_bits() < 64 {
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// no 32-bit encodings for 64-bit widths
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@@ -113,16 +113,6 @@ pub fn define(
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.build(),
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);
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let Scalar = &TypeVar::new(
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"scalar",
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"Any scalar value that can be used as a lane in a vector",
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TypeSetBuilder::new()
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.bools(Interval::All)
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.ints(Interval::All)
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.floats(Interval::All)
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.build(),
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);
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let Any = &TypeVar::new(
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"Any",
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"Any integer, float, boolean, or reference scalar or vector type",
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@@ -407,7 +397,7 @@ pub fn define(
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"resumable_trap",
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r#"
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A resumable trap.
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This instruction allows non-conditional traps to be used as non-terminal instructions.
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"#,
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)
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@@ -2772,8 +2762,8 @@ pub fn define(
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.operands_out(vec![a]),
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);
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let s = &operand_doc("s", Scalar, "A scalar value");
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let a = &operand_doc("a", TxN, "A vector value (i.e. held in an XMM register)");
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let a = &operand_doc("a", TxN, "A vector value");
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let s = &operand_doc("s", &TxN.lane_of(), "A scalar value");
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ig.push(
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Inst::new(
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