Add an Encoding meta-language class.

Start adding some RISC-V encodings too as a way of testing the ergonomics.

meta/target/riscv/__init__.py

@@ -25,11 +25,9 @@ RV32G / RV64G
 
 """
 
-from cretonne import Target, CPUMode
-import cretonne.base
+import defs
+import encodings
 
-target = Target('riscv', [cretonne.base.instructions])
+# Re-export the primary target definition.
+target = defs.target
 
-# CPU modes for 32-bit and 64-bit operation.
-RV32 = CPUMode('RV32', target)
-RV64 = CPUMode('RV64', target)

meta/target/riscv/defs.py

@@ -0,0 +1,14 @@
+"""
+RISC-V definitions.
+
+Commonly used definitions.
+"""
+
+from cretonne import Target, CPUMode
+import cretonne.base
+
+target = Target('riscv', [cretonne.base.instructions])
+
+# CPU modes for 32-bit and 64-bit operation.
+RV32 = CPUMode('RV32', target)
+RV64 = CPUMode('RV64', target)

meta/target/riscv/encodings.py

@@ -0,0 +1,21 @@
+"""
+RISC-V Encodings.
+"""
+from cretonne import base
+from cretonne.types import i32, i64
+from defs import RV32, RV64
+from recipes import OP, R
+
+# Basic arithmetic binary instructions are encoded in an R-type instruction.
+for inst,           f3,    f7 in [
+        (base.iadd, 0b000, 0b0000000),
+        (base.isub, 0b000, 0b0100000),
+        (base.ishl, 0b001, 0b0000000),
+        (base.ushr, 0b101, 0b0000000),
+        (base.sshr, 0b101, 0b0100000),
+        (base.bxor, 0b100, 0b0000000),
+        (base.bor,  0b110, 0b0000000),
+        (base.band, 0b111, 0b0000000)
+        ]:
+    RV32.enc(inst, i32, R, OP(f3, f7))
+    RV64.enc(inst, i64, R, OP(f3, f7))

meta/target/riscv/recipes.py

@@ -0,0 +1,44 @@
+"""
+RISC-V Encoding recipes.
+
+The encoding recipes defined here more or less correspond to the RISC-V native
+instruction formats described in the reference:
+
+    The RISC-V Instruction Set Manual
+    Volume I: User-Level ISA
+    Version 2.1
+"""
+from cretonne import EncRecipe
+from cretonne.formats import Binary
+
+# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
+# instructions have 11 as the two low bits, with bits 6:2 determining the base
+# opcode.
+#
+# Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
+# The functions below encode the encbits.
+
+def LOAD(funct3):
+    assert funct3 <= 0b111
+    return 0b00000 | (funct3 << 5)
+
+def STORE(funct3):
+    assert funct3 <= 0b111
+    return 0b01000 | (funct3 << 5)
+
+def BRANCH(funct3):
+    assert funct3 <= 0b111
+    return 0b11000 | (funct3 << 5)
+
+def OPIMM(funct3):
+    assert funct3 <= 0b111
+    return 0b00100 | (funct3 << 5)
+
+def OP(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01100 | (funct3 << 5) | (funct7 << 8)
+
+# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
+# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
+R = EncRecipe('R', Binary)