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cranelift: Remove copy instruction (#5125)

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This commit is contained in:
Afonso Bordado
2022-10-26 01:27:33 +01:00
committed by GitHub
parent b3333bf9ea
commit 4867813f77
12 changed files with 0 additions and 227 deletions
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21
cranelift/codegen/meta/src/shared/instructions.rs
View File

@@ -1470,27 +1470,6 @@ pub(crate) fn define(
.operands_out(vec![a]),
);
let x = &Operand::new("x", Any);
ig.push(
Inst::new(
"copy",
r#"
Register-register copy.
This instruction copies its input, preserving the value type.
A pure SSA-form program does not need to copy values, but this
instruction is useful for representing intermediate stages during
instruction transformations, and the register allocator needs a way of
representing register copies.
"#,
&formats.unary,
)
.operands_in(vec![x])
.operands_out(vec![a]),
);
let x = &Operand::new("x", TxN).with_doc("Vector to split");
let lo = &Operand::new("lo", &TxN.half_vector()).with_doc("Low-numbered lanes of `x`");
let hi = &Operand::new("hi", &TxN.half_vector()).with_doc("High-numbered lanes of `x`");

5
cranelift/codegen/src/ir/dfg.rs
View File

@@ -1467,10 +1467,5 @@ mod tests {
assert_eq!(pos.func.dfg.resolve_aliases(c2), c2);
assert_eq!(pos.func.dfg.resolve_aliases(c), c2);
// Make a copy of the alias.
let c3 = pos.ins().copy(c);
// This does not see through copies.
assert_eq!(pos.func.dfg.resolve_aliases(c3), c3);
}
}

5
cranelift/codegen/src/isa/aarch64/lower.isle
View File

@@ -2265,11 +2265,6 @@
(u8_from_uimm8 lane)))
(mov_vec_elem vec val lane 0 (vector_size vty)))
;;; Rules for `copy` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (copy x))
x)
;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (stack_addr stack_slot offset))

2
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -157,8 +157,6 @@ pub(crate) fn lower_insn_to_regs(
Opcode::IsNull | Opcode::IsInvalid => implemented_in_isle(ctx),
Opcode::Copy => implemented_in_isle(ctx),
Opcode::Ireduce => implemented_in_isle(ctx),
Opcode::Bmask => implemented_in_isle(ctx),

4
cranelift/codegen/src/isa/riscv64/lower.isle
View File

@@ -535,10 +535,6 @@
(_ Unit (emit (MInst.AtomicCas (gen_atomic_offset p ty) t0 dst (ext_int_if_need $false e ty) (gen_atomic_p p ty) x ty))))
(writable_reg_to_reg dst)))
;;;;; Rules for `copy`;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (copy x)))
(gen_move2 x ty ty))
;;;;; Rules for `ireduce`;;;;;;;;;;;;;;;;;
(rule
(lower (has_type ty (ireduce x)))

6
cranelift/codegen/src/isa/s390x/lower.isle
View File

@@ -46,12 +46,6 @@
(invalid_reg))
;;;; Rules for `copy` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (copy x))
x)
;;;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (vr128_ty ty) (iconcat x y)))

1
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -43,7 +43,6 @@ impl LowerBackend for S390xBackend {
match op {
Opcode::Nop
| Opcode::Copy
| Opcode::Iconst
| Opcode::F32const
| Opcode::F64const

4
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -559,10 +559,6 @@ fn lower_insn_to_regs(
panic!("table_addr should have been removed by legalization!");
}
Opcode::Copy => {
panic!("Unused opcode should not be encountered.");
}
Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
panic!("trapz / trapnz / resumable_trapnz should have been removed by legalization!");
}

81
cranelift/filetests/filetests/runtests/copy.clif
View File

@@ -1,81 +0,0 @@
test interpret
test run
target aarch64
target s390x
; x86_64 regards this as an unused opcode.
function %copy_i8(i8) -> i8 {
block0(v0: i8):
v1 = copy v0
return v1
}
; run: %copy_i8(0) == 0
; run: %copy_i8(255) == 255
; run: %copy_i8(-1) == -1
; run: %copy_i8(127) == 127
function %copy_i16(i16) -> i16 {
block0(v0: i16):
v1 = copy v0
return v1
}
; run: %copy_i16(0) == 0
; run: %copy_i16(65535) == 65535
; run: %copy_i16(-1) == -1
; run: %copy_i16(127) == 127
function %copy_i32(i32) -> i32 {
block0(v0: i32):
v1 = copy v0
return v1
}
; run: %copy_i32(0) == 0
; run: %copy_i32(4294967295) == 4294967295
; run: %copy_i32(-1) == -1
; run: %copy_i32(127) == 127
function %copy_i64(i64) -> i64 {
block0(v0: i64):
v1 = copy v0
return v1
}
; run: %copy_i64(0) == 0
; run: %copy_i64(18446744073709551615) == 18446744073709551615
; run: %copy_i64(-1) == -1
; run: %copy_i64(127) == 127
function %copy_f32(f32) -> f32 {
block0(v0: f32):
v1 = copy v0
return v1
}
; run: %copy_f32(0x1.0) == 0x1.0
; run: %copy_f32(0x1.0p10) == 0x1.0p10
; run: %copy_f32(0x0.0) == 0x0.0
; run: %copy_f32(-0x0.0) == -0x0.0
; run: %copy_f32(+Inf) == +Inf
; run: %copy_f32(-Inf) == -Inf
; run: %copy_f32(0x1.000002p-23) == 0x1.000002p-23
; run: %copy_f32(0x1.fffffep127) == 0x1.fffffep127
; run: %copy_f32(0x1.000000p-126) == 0x1.000000p-126
; run: %copy_f32(0x0.800002p-126) == 0x0.800002p-126
; run: %copy_f32(-0x0.800000p-126) == -0x0.800000p-126
function %copy_f64(f64) -> f64 {
block0(v0: f64):
v1 = copy v0
return v1
}
; run: %copy_f64(0x2.0) == 0x2.0
; run: %copy_f64(0x1.0p11) == 0x1.0p11
; run: %copy_f64(0x0.0) == 0x0.0
; run: %copy_f64(-0x0.0) == -0x0.0
; run: %copy_f64(+Inf) == +Inf
; run: %copy_f64(-Inf) == -Inf
; run: %copy_f64(0x1.0000000000002p-52) == 0x1.0000000000002p-52
; run: %copy_f64(0x1.fffffffffffffp1023) == 0x1.fffffffffffffp1023
; run: %copy_f64(0x1.0000000000000p-1022) == 0x1.0000000000000p-1022
; run: %copy_f64(0x0.8000000000002p-1022) == 0x0.8000000000002p-1022
; run: %copy_f64(-0x0.8000000000000p-1022) == -0x0.8000000000000p-1022

40
cranelift/filetests/filetests/runtests/simd-copy-64bit.clif
View File

@@ -1,40 +0,0 @@
test interpret
test run
target aarch64
; x86_64 regards this as an unused opcode.
; s390x does not support 64-bit vectors.
function %copy_i8x8(i8x8) -> i8x8 {
block0(v0: i8x8):
v1 = copy v0
return v1
}
; run: %copy_i8x8([0 0 255 255 -1 -1 127 128]) == [0 0 255 255 -1 -1 127 128]
function %copy_i16x4(i16x4) -> i16x4 {
block0(v0: i16x4):
v1 = copy v0
return v1
}
; run: %copy_i16x4([0 65535 -1 127]) == [0 65535 -1 127]
function %copy_i32x2(i32x2) -> i32x2 {
block0(v0: i32x2):
v1 = copy v0
return v1
}
; run: %copy_i32x2([0 4294967295]) == [0 4294967295]
; run: %copy_i32x2([-1 127]) == [-1 127]
function %copy_f32x2(f32x2) -> f32x2 {
block0(v0: f32x2):
v1 = copy v0
return v1
}
; run: %copy_f32x2([0x1.0 0x1.0p10]) == [0x1.0 0x1.0p10]
; run: %copy_f32x2([0x0.0 -0x0.0]) == [0x0.0 -0x0.0]
; run: %copy_f32x2([+Inf -Inf]) == [+Inf -Inf]
; run: %copy_f32x2([0x1.000002p-23 0x1.fffffep127]) == [0x1.000002p-23 0x1.fffffep127]
; run: %copy_f32x2([0x1.000000p-126 0x0.800002p-126]) == [0x1.000000p-126 0x0.800002p-126]
; run: %copy_f32x2([-0x0.800000p-126 -0x0.800000p-126]) == [-0x0.800000p-126 -0x0.800000p-126]

57
cranelift/filetests/filetests/runtests/simd-copy.clif
View File

@@ -1,57 +0,0 @@
test interpret
test run
target aarch64
target s390x
; x86_64 regards this as an unused opcode.
function %copy_i8x16(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = copy v0
return v1
}
; run: %copy_i8x16([0 0 255 255 -1 -1 127 128 0 0 255 255 -1 -1 127 128]) == [0 0 255 255 -1 -1 127 128 0 0 255 255 -1 -1 127 128]
function %copy_i16x8(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = copy v0
return v1
}
; run: %copy_i16x8([0 65535 -1 127 0 65535 -1 128]) == [0 65535 -1 127 0 65535 -1 128]
function %copy_i32x4(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = copy v0
return v1
}
; run: %copy_i32x4([0 4294967295 -1 127]) == [0 4294967295 -1 127]
function %copy_i64x2(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = copy v0
return v1
}
; run: %copy_i64x2([0 18446744073709551615]) == [0 18446744073709551615]
; run: %copy_i64x2([-1 127]) == [-1 127]
function %copy_f32x4(f32x4) -> f32x4 {
block0(v0: f32x4):
v1 = copy v0
return v1
}
; run: %copy_f32x4([0x1.0 0x1.0p10 0x0.0 -0x0.0]) == [0x1.0 0x1.0p10 0x0.0 -0x0.0]
; run: %copy_f32x4([+Inf -Inf 0x1.000002p-23 0x1.fffffep127]) == [+Inf -Inf 0x1.000002p-23 0x1.fffffep127]
; run: %copy_f32x4([0x1.000000p-126 0x0.800002p-126 -0x0.800000p-126 -0x0.800000p-126]) == [0x1.000000p-126 0x0.800002p-126 -0x0.800000p-126 -0x0.800000p-126]
function %copy_f64x2(f64x2) -> f64x2 {
block0(v0: f64x2):
v1 = copy v0
return v1
}
; run: %copy_f64x2([0x2.0 0x1.0p11]) == [0x2.0 0x1.0p11]
; run: %copy_f64x2([0x0.0 -0x0.0]) == [0x0.0 -0x0.0]
; run: %copy_f64x2([+Inf -Inf]) == [+Inf -Inf]
; run: %copy_f64x2([0x1.0000000000002p-52 0x1.fffffffffffffp1023]) == [0x1.0000000000002p-52 0x1.fffffffffffffp1023]
; run: %copy_f64x2([0x1.0000000000000p-1022 0x0.8000000000002p-1022]) == [0x1.0000000000000p-1022 0x0.8000000000002p-1022]
; run: %copy_f64x2([-0x0.8000000000000p-1022 -0x0.8000000000000p-1022]) == [-0x0.8000000000000p-1022 -0x0.8000000000000p-1022]

1
cranelift/interpreter/src/step.rs
View File

@@ -552,7 +552,6 @@ where
let mask_b = Value::and(Value::not(arg(0)?)?, arg(2)?)?;
assign(Value::or(mask_a, mask_b)?)
}
Opcode::Copy => assign(arg(0)?),
Opcode::Icmp => assign(icmp(
ctrl_ty,
inst.cond_code().unwrap(),