From 471c1e32a436a4ff5f3bc62a81a95820ccc0f86f Mon Sep 17 00:00:00 2001 From: Nick Fitzgerald Date: Wed, 8 Dec 2021 15:37:24 -0800 Subject: [PATCH] Consolidate `XmmRmR`-based instructions together --- cranelift/codegen/src/isa/x64/inst.isle | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle index cd9a08c068..dc3c6775b7 100644 --- a/cranelift/codegen/src/isa/x64/inst.isle +++ b/cranelift/codegen/src/isa/x64/inst.isle @@ -953,6 +953,16 @@ (_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Movapd) (RegMem.Reg mask) mask2)))) (xmm_rm_r $F64X2 (SseOpcode.Blendvpd) src1 src2))) +;; Helper for creating `movsd` instructions. +(decl movsd (Reg RegMem) Reg) +(rule (movsd src1 src2) + (xmm_rm_r $I8X16 (SseOpcode.Movsd) src1 src2)) + +;; Helper for creating `movlhps` instructions. +(decl movlhps (Reg RegMem) Reg) +(rule (movlhps src1 src2) + (xmm_rm_r $I8X16 (SseOpcode.Movlhps) src1 src2)) + ;; Helper for creating `MInst.XmmRmRImm` instructions. (decl xmm_rm_r_imm (SseOpcode Reg RegMem u8 OperandSize) Reg) (rule (xmm_rm_r_imm op src1 src2 imm size) @@ -1146,13 +1156,3 @@ (decl insertps (Reg RegMem u8) Reg) (rule (insertps src1 src2 lane) (xmm_rm_r_imm (SseOpcode.Insertps) src1 src2 lane (OperandSize.Size32))) - -;; Helper for creating `movsd` instructions. -(decl movsd (Reg RegMem) Reg) -(rule (movsd src1 src2) - (xmm_rm_r $I8X16 (SseOpcode.Movsd) src1 src2)) - -;; Helper for creating `movlhps` instructions. -(decl movlhps (Reg RegMem) Reg) -(rule (movlhps src1 src2) - (xmm_rm_r $I8X16 (SseOpcode.Movlhps) src1 src2))