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Generate instruction unwrapping code for binemit recipes.

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Generate code to:

- Unwrap the instruction and generate an error if the instruction format
  doesn't match the recipe.
- Look up the value locations of register and stack arguments.

The recipe_* functions in the ISA binemit modules now take these
unwrapped items as arguments.

Also add an optional `emit` argument to the EncRecipe constructor which
makes it possible to provide inline Rust code snippets for code
emission. This requires a lot less boilerplate than recipe_* functions.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-07 11:33:38 -07:00
parent 814d076936
commit 464f2625d4
6 changed files with 435 additions and 419 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/cretonne/meta/cdsl/isa.py
View File

@@ -202,6 +202,7 @@ class EncRecipe(object):
:param: branch_range `(origin, bits)` range for branches.
:param: instp Instruction predicate.
:param: isap ISA predicate.
:param: emit Rust code for binary emission.
"""
def __init__(
@@ -213,7 +214,8 @@ class EncRecipe(object):
outs, # type: ConstraintSeq
branch_range=None, # type: BranchRange
instp=None, # type: PredNode
isap=None # type: PredNode
isap=None, # type: PredNode
emit=None # type: str
):
# type: (...) -> None
self.name = name
@@ -223,6 +225,7 @@ class EncRecipe(object):
self.branch_range = branch_range
self.instp = instp
self.isap = isap
self.emit = emit
if instp:
assert instp.predicate_context() == format
self.number = None # type: int

105
lib/cretonne/meta/gen_binemit.py
View File

@@ -3,15 +3,108 @@ Generate binary emission code for each ISA.
"""
from __future__ import absolute_import
from cdsl.registers import RegClass, Stack
import srcgen
try:
from typing import Sequence, List # noqa
from cdsl.isa import TargetISA # noqa
from cdsl.isa import TargetISA, EncRecipe # noqa
except ImportError:
pass
def gen_recipe(recipe, fmt):
# type: (EncRecipe, srcgen.Formatter) -> None
"""
Generate code to handle a single recipe.
- Unpack the instruction data, knowing the format.
- Determine register locations for operands with register constraints.
- Determine stack slot locations for operands with stack constraints.
- Call hand-written code for the actual emission.
"""
iform = recipe.format
nvops = iform.num_value_operands
want_args = any(isinstance(i, RegClass) or isinstance(i, Stack)
for i in recipe.ins)
assert not want_args or nvops > 0
want_outs = any(isinstance(o, RegClass) or isinstance(o, Stack)
for o in recipe.outs)
# First unpack the instruction.
with fmt.indented(
'if let InstructionData::{} {{'.format(iform.name),
'}'):
for f in iform.imm_fields:
fmt.line('{},'.format(f.member))
if want_args:
if iform.has_value_list or nvops > 1:
fmt.line('ref args,')
else:
fmt.line('arg,')
fmt.line('..')
fmt.outdented_line('} = func.dfg[inst] {')
# Normalize to an `args` array.
if want_args:
if iform.has_value_list:
fmt.line('let args = args.as_slice(&func.dfg.value_lists);')
elif nvops == 1:
fmt.line('let args = [arg];')
# Unwrap interesting input arguments.
# Don't bother with fixed registers.
args = ''
for i, arg in enumerate(recipe.ins):
if isinstance(arg, RegClass):
v = 'in_reg{}'.format(i)
args += ', ' + v
fmt.line(
'let {} = func.locations[args[{}]].unwrap_reg();'
.format(v, i))
elif isinstance(arg, Stack):
v = 'in_ss{}'.format(i)
args += ', ' + v
fmt.line(
'let {} = func.locations[args[{}]].unwrap_stack();'
.format(v, i))
# Pass arguments in this order: inputs, imm_fields, outputs.
for f in iform.imm_fields:
args += ', ' + f.member
# Unwrap interesting output arguments.
if want_outs:
if len(recipe.outs) == 1:
fmt.line('let results = [func.dfg.first_result(inst)];')
else:
fmt.line('let results = func.dfg.inst_results(inst);')
for i, res in enumerate(recipe.outs):
if isinstance(res, RegClass):
v = 'out_reg{}'.format(i)
args += ', ' + v
fmt.line(
'let {} = func.locations[results[{}]].unwrap_reg();'
.format(v, i))
elif isinstance(res, Stack):
v = 'out_ss{}'.format(i)
args += ', ' + v
fmt.line(
'let {} = func.locations[results[{}]].unwrap_stack();'
.format(v, i))
# Call hand-written code. If the recipe contains a code snippet, use
# that. Otherwise cal a recipe function in the target ISA's binemit
# module.
if recipe.emit is None:
fmt.format(
'return recipe_{}(func, inst, sink, bits{});',
recipe.name.lower(), args)
else:
fmt.multi_line(recipe.emit)
fmt.line('return;')
def gen_isa(isa, fmt):
# type: (TargetISA, srcgen.Formatter) -> None
"""
@@ -28,14 +121,18 @@ def gen_isa(isa, fmt):
'(func: &Function, inst: Inst, _sink: &mut CS) {', '}'):
fmt.line('bad_encoding(func, inst)')
else:
fmt.line('#[allow(unused_variables, unreachable_code)]')
with fmt.indented(
'pub fn emit_inst<CS: CodeSink + ?Sized>'
'(func: &Function, inst: Inst, sink: &mut CS) {', '}'):
fmt.line('let bits = func.encodings[inst].bits();')
with fmt.indented('match func.encodings[inst].recipe() {', '}'):
for i, recipe in enumerate(isa.all_recipes):
fmt.line('{} => recipe_{}(func, inst, sink),'.format(
i, recipe.name.lower()))
fmt.line('_ => bad_encoding(func, inst),')
fmt.comment(recipe.name)
with fmt.indented('{} => {{'.format(i), '}'):
gen_recipe(recipe, fmt)
fmt.line('_ => {}')
fmt.line('bad_encoding(func, inst);')
def generate(isas, out_dir):

91
lib/cretonne/meta/isa/riscv/recipes.py
View File

@@ -92,68 +92,123 @@ def LUI():
# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
R = EncRecipe('R', Binary, size=4, ins=(GPR, GPR), outs=GPR)
R = EncRecipe(
'R', Binary, size=4, ins=(GPR, GPR), outs=GPR,
emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
# R-type with an immediate shift amount instead of rs2.
Rshamt = EncRecipe('Rshamt', BinaryImm, size=4, ins=GPR, outs=GPR)
Rshamt = EncRecipe(
'Rshamt', BinaryImm, size=4, ins=GPR, outs=GPR,
emit='put_rshamt(bits, in_reg0, imm.into(), out_reg0, sink);')
# R-type encoding of an integer comparison.
Ricmp = EncRecipe('Ricmp', IntCompare, size=4, ins=(GPR, GPR), outs=GPR)
Ricmp = EncRecipe(
'Ricmp', IntCompare, size=4, ins=(GPR, GPR), outs=GPR,
emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
I = EncRecipe(
'I', BinaryImm, size=4, ins=GPR, outs=GPR,
instp=IsSignedInt(BinaryImm.imm, 12))
instp=IsSignedInt(BinaryImm.imm, 12),
emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
# I-type instruction with a hardcoded %x0 rs1.
Iz = EncRecipe(
'Iz', UnaryImm, size=4, ins=(), outs=GPR,
instp=IsSignedInt(UnaryImm.imm, 12))
instp=IsSignedInt(UnaryImm.imm, 12),
emit='put_i(bits, 0, imm.into(), out_reg0, sink);')
# I-type encoding of an integer comparison.
Iicmp = EncRecipe(
'Iicmp', IntCompareImm, size=4, ins=GPR, outs=GPR,
instp=IsSignedInt(IntCompareImm.imm, 12))
instp=IsSignedInt(IntCompareImm.imm, 12),
emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
# I-type encoding for `jalr` as a return instruction. We won't use the
# immediate offset.
# The variable return values are not encoded.
Iret = EncRecipe('Iret', MultiAry, size=4, ins=(), outs=())
Iret = EncRecipe(
'Iret', MultiAry, size=4, ins=(), outs=(),
emit='''
// Return instructions are always a jalr to %x1.
// The return address is provided as a special-purpose link argument.
put_i(bits,
1, // rs1 = %x1
0, // no offset.
0, // rd = %x0: no address written.
sink);
''')
# I-type encoding for `jalr` as an indirect call.
Icall = EncRecipe('Icall', IndirectCall, size=4, ins=GPR, outs=())
Icall = EncRecipe(
'Icall', IndirectCall, size=4, ins=GPR, outs=(),
emit='''
// Indirect instructions are jalr with rd=%x1.
put_i(bits,
in_reg0,
0, // no offset.
1, // rd = %x1: link register.
sink);
''')
# Copy of a GPR is implemented as addi x, 0.
Icopy = EncRecipe('Icopy', Unary, size=4, ins=GPR, outs=GPR)
Icopy = EncRecipe(
'Icopy', Unary, size=4, ins=GPR, outs=GPR,
emit='put_i(bits, in_reg0, 0, out_reg0, sink);')
# U-type instructions have a 20-bit immediate that targets bits 12-31.
U = EncRecipe(
'U', UnaryImm, size=4, ins=(), outs=GPR,
instp=IsSignedInt(UnaryImm.imm, 32, 12))
instp=IsSignedInt(UnaryImm.imm, 32, 12),
emit='put_u(bits, imm.into(), out_reg0, sink);')
# UJ-type unconditional branch instructions.
UJ = EncRecipe('UJ', Jump, size=4, ins=(), outs=(), branch_range=(0, 21))
UJcall = EncRecipe('UJcall', Call, size=4, ins=(), outs=())
UJ = EncRecipe(
'UJ', Jump, size=4, ins=(), outs=(), branch_range=(0, 21),
emit='''
let dest = func.offsets[destination] as i64;
let disp = dest - sink.offset() as i64;
put_uj(bits, disp, 0, sink);
''')
UJcall = EncRecipe(
'UJcall', Call, size=4, ins=(), outs=(),
emit='''
sink.reloc_func(RelocKind::Call.into(), func_ref);
// rd=%x1 is the standard link register.
put_uj(bits, 0, 1, sink);
''')
# SB-type branch instructions.
# TODO: These instructions have a +/- 4 KB branch range. How to encode that
# constraint?
SB = EncRecipe(
'SB', BranchIcmp, size=4,
ins=(GPR, GPR), outs=(),
branch_range=(0, 13))
branch_range=(0, 13),
emit='''
let dest = func.offsets[destination] as i64;
let disp = dest - sink.offset() as i64;
put_sb(bits, disp, in_reg0, in_reg1, sink);
''')
# SB-type branch instruction with rs2 fixed to zero.
SBzero = EncRecipe(
'SBzero', Branch, size=4,
ins=(GPR), outs=(),
branch_range=(0, 13))
branch_range=(0, 13),
emit='''
let dest = func.offsets[destination] as i64;
let disp = dest - sink.offset() as i64;
put_sb(bits, disp, in_reg0, 0, sink);
''')
# Spill of a GPR.
GPsp = EncRecipe(
'GPsp', Unary, size=4,
ins=GPR, outs=Stack(GPR))
ins=GPR, outs=Stack(GPR),
emit='unimplemented!();')
# Fill of a GPR.
GPfi = EncRecipe(
'GPfi', Unary, size=4,
ins=Stack(GPR), outs=GPR)
ins=Stack(GPR), outs=GPR,
emit='unimplemented!();')