Bump regalloc.rs to 0.0.26;

And adapt to regalloc.rs API change to provide the exact number of vregs.

Cargo.lock

@@ -1663,9 +1663,9 @@ dependencies = [
 
 [[package]]
 name = "regalloc"
-version = "0.0.25"
+version = "0.0.26"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cca5b48c9db66c5ba084e4660b4c0cfe8b551a96074bc04b7c11de86ad0bf1f9"
+checksum = "7c03092d79e0fd610932d89ed53895a38c0dd3bcd317a0046e69940de32f1d95"
 dependencies = [
  "log",
  "rustc-hash",

cranelift/codegen/Cargo.toml

@@ -25,7 +25,7 @@ smallvec = { version = "1.0.0" }
 thiserror = "1.0.4"
 byteorder = { version = "1.3.2", default-features = false }
 peepmatic-runtime = { path = "../peepmatic/crates/runtime", optional = true, version = "0.1.0" }
-regalloc = "0.0.25"
+regalloc = "0.0.26"
 # It is a goal of the cranelift-codegen crate to have minimal external dependencies.
 # Please don't add any unless they are essential to the task of creating binary
 # machine code. Integration tests that need external dependencies can be

cranelift/codegen/src/machinst/vcode.rs

@@ -465,8 +465,8 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         insn.is_move()
     }
 
-    fn get_vreg_count_estimate(&self) -> Option<usize> {
-        Some(self.vreg_types.len())
+    fn get_num_vregs(&self) -> usize {
+        self.vreg_types.len()
     }
 
     fn get_spillslot_size(&self, regclass: RegClass, vreg: VirtualReg) -> u32 {

cranelift/filetests/filetests/vcode/aarch64/saturating-ops.clif

@@ -25,10 +25,10 @@ block0(v0: i8, v1: i8):
 
 ; check: stp fp, lr, [sp, #-16]!
 ; nextln: mov fp, sp
-; nextln: uxtb x2, w0
-; nextln: uxtb x0, w1
-; nextln: mov v0.d[0], x2
-; nextln: mov v1.d[0], x0
+; nextln: uxtb x0, w0
+; nextln: uxtb x1, w1
+; nextln: mov v0.d[0], x0
+; nextln: mov v1.d[0], x1
 ; nextln: uqadd d0, d0, d1
 ; nextln: mov x0, v0.d[0]
 ; nextln: mov sp, fp

cranelift/filetests/filetests/vcode/aarch64/shift-rotate.clif

@@ -368,10 +368,10 @@ block0(v0: i16):
 
 ; check: stp fp, lr, [sp, #-16]!
 ; nextln: mov fp, sp
-; nextln: uxth w1, w0
-; nextln: lsr w0, w1, #6
-; nextln: lsl w1, w1, #10
-; nextln: orr w0, w1, w0
+; nextln: uxth w0, w0
+; nextln: lsr w1, w0, #6
+; nextln: lsl w0, w0, #10
+; nextln: orr w0, w0, w1
 ; nextln: mov sp, fp
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
@@ -385,10 +385,10 @@ block0(v0: i8):
 
 ; check:  stp fp, lr, [sp, #-16]!
 ; nextln:  mov fp, sp
-; nextln:  uxtb w1, w0
-; nextln:  lsr w0, w1, #5
-; nextln:  lsl w1, w1, #3
-; nextln:  orr w0, w1, w0
+; nextln:  uxtb w0, w0
+; nextln:  lsr w1, w0, #5
+; nextln:  lsl w0, w0, #3
+; nextln:  orr w0, w0, w1
 ; nextln:  mov sp, fp
 ; nextln:  ldp fp, lr, [sp], #16
 ; nextln:  ret