From 452d85485530875b81f5bd4c8557e2994b36ed1d Mon Sep 17 00:00:00 2001 From: Andrew Brown Date: Mon, 28 Sep 2020 13:45:15 -0700 Subject: [PATCH] [machinst x64]: demonstrate that packed register moves are elided --- .../filetests/isa/x64/move-elision.clif | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 cranelift/filetests/filetests/isa/x64/move-elision.clif diff --git a/cranelift/filetests/filetests/isa/x64/move-elision.clif b/cranelift/filetests/filetests/isa/x64/move-elision.clif new file mode 100644 index 0000000000..45f07b98d4 --- /dev/null +++ b/cranelift/filetests/filetests/isa/x64/move-elision.clif @@ -0,0 +1,21 @@ +test compile +set enable_simd +target x86_64 skylake +feature "experimental_x64" + +function %move_registers(i32x4) -> b8x16 { +block0(v0: i32x4): + ;; In the x64 backend, all of these pseudo-instructions are lowered to moves between registers (e.g. MOVAPD, MOVDQA, + ;; etc.). Because these have been marked as moves, no instructions are emitted by this function besides the prologue + ;; and epilogue. + v1 = raw_bitcast.f32x4 v0 + v2 = raw_bitcast.f64x2 v1 + v3 = raw_bitcast.b8x16 v2 + return v3 +} +; check: pushq %rbp +; nextln: movq %rsp, %rbp +; nextln: movq %rbp, %rsp +; nextln: popq %rbp +; nextln: ret +