Add x86 implementation of fcvt_from_sint

cranelift/codegen/meta/src/isa/x86/encodings.rs

@@ -1568,6 +1568,7 @@ fn define_simd(
     let copy_nop = shared.by_name("copy_nop");
     let fadd = shared.by_name("fadd");
     let fcmp = shared.by_name("fcmp");
+    let fcvt_from_sint = shared.by_name("fcvt_from_sint");
     let fdiv = shared.by_name("fdiv");
     let fill = shared.by_name("fill");
     let fill_nop = shared.by_name("fill_nop");
@@ -1790,6 +1791,14 @@ fn define_simd(
         }
     }
 
+    // SIMD conversions
+    {
+        let fcvt_from_sint_32 = fcvt_from_sint
+            .bind(vector(F32, sse_vector_size))
+            .bind(vector(I32, sse_vector_size));
+        e.enc_both(fcvt_from_sint_32, rec_furm.opcodes(&CVTDQ2PS));
+    }
+
     // SIMD vconst for special cases (all zeroes, all ones)
     // this must be encoded prior to the MOVUPS implementation (below) so the compiler sees this
     // encoding first

cranelift/codegen/meta/src/isa/x86/opcodes.rs

@@ -77,6 +77,10 @@ pub static CMPPD: [u8; 3] = [0x66, 0x0f, 0xc2];
 /// imm8 as comparison predicate (SSE).
 pub static CMPPS: [u8; 2] = [0x0f, 0xc2];
 
+/// Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision
+/// floating-point values in xmm1 (SSE2).
+pub static CVTDQ2PS: [u8; 2] = [0x0f, 0x5b];
+
 /// Convert scalar double-precision floating-point value to scalar single-precision
 /// floating-point value.
 pub static CVTSD2SS: [u8; 3] = [0xf2, 0x0f, 0x5a];