Remove more old backend ISA concepts (#3402)

This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate.

Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!

cranelift/filetests/filetests/parser/tiny.clif

@@ -183,42 +183,6 @@ block0(v1: i32):
 ; nextln:     store_complex v3, v1+v2
 ; nextln:     store_complex v3, v1+v2+1
 
-; Register diversions.
-; This test file has no ISA, so we can unly use register unit numbers.
-function %diversion(i32) {
-    ss0 = spill_slot 4
-
-block0(v1: i32):
-    regmove v1, %10 -> %20
-    regmove v1, %20 -> %10
-    regspill v1, %10 -> ss0
-    regfill v1, ss0 -> %10
-    return
-}
-; sameln: function %diversion(i32) fast {
-; nextln:     ss0 = spill_slot 4
-; check: block0(v1: i32):
-; nextln:     regmove v1, %10 -> %20
-; nextln:     regmove v1, %20 -> %10
-; nextln:     regspill v1, %10 -> ss0
-; nextln:     regfill v1, ss0 -> %10
-; nextln:     return
-; nextln: }
-
-; Register copies.
-function %copy_special() {
-block0:
-    copy_special %10 -> %20
-    copy_special %20 -> %10
-    return
-}
-; sameln: function %copy_special() fast {
-; nextln: block0:
-; nextln:     copy_special %10 -> %20
-; nextln:     copy_special %20 -> %10
-; nextln:     return
-; nextln: }
-
 function %cond_traps(i32) {
 block0(v0: i32):
     trapz v0, stk_ovf