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Remove more old backend ISA concepts (#3402)

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This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate.

Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
This commit is contained in:
Benjamin Bouvier
2021-10-04 10:36:12 +02:00
committed by GitHub
parent 76afcab0c2
commit 43a86f14d5
71 changed files with 302 additions and 2059 deletions
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13
cranelift/codegen/src/binemit/memorysink.rs
View File

@@ -15,9 +15,7 @@
//! `CodeSink::put*` methods, so the performance impact of the virtual callbacks is less severe.
use super::{Addend, CodeInfo, CodeOffset, CodeSink, Reloc};
use crate::binemit::stack_map::StackMap;
use crate::ir::entities::Value;
use crate::ir::{ConstantOffset, ExternalName, Function, JumpTable, Opcode, SourceLoc, TrapCode};
use crate::isa::TargetIsa;
use crate::ir::{ConstantOffset, ExternalName, JumpTable, Opcode, SourceLoc, TrapCode};
use core::ptr::write_unaligned;
/// A `CodeSink` that writes binary machine code directly into memory.
@@ -38,7 +36,6 @@ pub struct MemoryCodeSink<'a> {
offset: isize,
relocs: &'a mut dyn RelocSink,
traps: &'a mut dyn TrapSink,
stack_maps: &'a mut dyn StackMapSink,
/// Information about the generated code and read-only data.
pub info: CodeInfo,
}
@@ -54,7 +51,6 @@ impl<'a> MemoryCodeSink<'a> {
data: *mut u8,
relocs: &'a mut dyn RelocSink,
traps: &'a mut dyn TrapSink,
stack_maps: &'a mut dyn StackMapSink,
) -> Self {
Self {
data,
@@ -67,7 +63,6 @@ impl<'a> MemoryCodeSink<'a> {
},
relocs,
traps,
stack_maps,
}
}
}
@@ -174,12 +169,6 @@ impl<'a> CodeSink for MemoryCodeSink<'a> {
self.info.total_size = self.offset();
}
fn add_stack_map(&mut self, val_list: &[Value], func: &Function, isa: &dyn TargetIsa) {
let ofs = self.offset();
let stack_map = StackMap::from_values(&val_list, func, isa);
self.stack_maps.add_stack_map(ofs, stack_map);
}
fn add_call_site(&mut self, opcode: Opcode, loc: SourceLoc) {
debug_assert!(
opcode.is_call(),

4
cranelift/codegen/src/binemit/mod.rs
View File

@@ -11,7 +11,6 @@ pub use self::memorysink::{
TrapSink,
};
pub use self::stack_map::StackMap;
use crate::ir::entities::Value;
use crate::ir::{
ConstantOffset, ExternalName, Function, Inst, JumpTable, Opcode, SourceLoc, TrapCode,
};
@@ -169,9 +168,6 @@ pub trait CodeSink {
/// Read-only data output is complete, we're done.
fn end_codegen(&mut self);
/// Add a stack map at the current code offset.
fn add_stack_map(&mut self, _: &[Value], _: &Function, _: &dyn TargetIsa);
/// Add a call site for a call with the given opcode, returning at the current offset.
fn add_call_site(&mut self, _: Opcode, _: SourceLoc) {
// Default implementation doesn't need to do anything.

53
cranelift/codegen/src/binemit/stack_map.rs
View File

@@ -1,6 +1,4 @@
use crate::bitset::BitSet;
use crate::ir;
use crate::isa::TargetIsa;
use alloc::vec::Vec;
type Num = u32;
@@ -76,57 +74,6 @@ pub struct StackMap {
}
impl StackMap {
/// Create a `StackMap` based on where references are located on a
/// function's stack.
pub fn from_values(
args: &[ir::entities::Value],
func: &ir::Function,
isa: &dyn TargetIsa,
) -> Self {
let loc = &func.locations;
let mut live_ref_in_stack_slot = crate::HashSet::new();
// References can be in registers, and live registers values are pushed onto the stack before calls and traps.
// TODO: Implement register maps. If a register containing a reference is spilled and reused after a safepoint,
// it could contain a stale reference value if the garbage collector relocated the value.
for val in args {
if let Some(value_loc) = loc.get(*val) {
match *value_loc {
ir::ValueLoc::Stack(stack_slot) => {
live_ref_in_stack_slot.insert(stack_slot);
}
_ => {}
}
}
}
let stack = &func.stack_slots;
let info = func.stack_slots.layout_info.unwrap();
// Refer to the doc comment for `StackMap` above to understand the
// bitmap representation used here.
let map_size = (info.frame_size + info.inbound_args_size) as usize;
let word_size = isa.pointer_bytes() as usize;
let num_words = map_size / word_size;
let mut vec = alloc::vec::Vec::with_capacity(num_words);
vec.resize(num_words, false);
for (ss, ssd) in stack.iter() {
if !live_ref_in_stack_slot.contains(&ss)
|| ssd.kind == ir::stackslot::StackSlotKind::OutgoingArg
{
continue;
}
debug_assert!(ssd.size as usize == word_size);
let bytes_from_bottom = info.frame_size as i32 + ssd.offset.unwrap();
let words_from_bottom = (bytes_from_bottom as usize) / word_size;
vec[words_from_bottom] = true;
}
Self::from_slice(&vec)
}
/// Create a vec of Bitsets from a slice of bools.
pub fn from_slice(vec: &[bool]) -> Self {
let len = vec.len();

4
cranelift/codegen/src/cfg_printer.rs
View File

@@ -51,11 +51,11 @@ impl<'a> CFGPrinter<'a> {
for block in &self.func.layout {
write!(w, " {} [shape=record, label=\"{{", block)?;
crate::write::write_block_header(w, self.func, None, block, 4)?;
crate::write::write_block_header(w, self.func, block, 4)?;
// Add all outgoing branch instructions to the label.
for inst in self.func.layout.block_likely_branches(block) {
write!(w, " | <{}>", inst)?;
PlainWriter.write_instruction(w, self.func, &aliases, None, inst, 0)?;
PlainWriter.write_instruction(w, self.func, &aliases, inst, 0)?;
}
writeln!(w, "}}\"]")?
}

4
cranelift/codegen/src/context.rs
View File

@@ -140,7 +140,7 @@ impl Context {
log::debug!(
"Compiling (opt level {:?}):\n{}",
opt_level,
self.func.display(isa)
self.func.display()
);
self.compute_cfg();
@@ -196,7 +196,7 @@ impl Context {
stack_maps: &mut dyn StackMapSink,
) -> CodeInfo {
let _tt = timing::binemit();
let mut sink = MemoryCodeSink::new(mem, relocs, traps, stack_maps);
let mut sink = MemoryCodeSink::new(mem, relocs, traps);
let result = self
.mach_compile_result
.as_ref()

2
cranelift/codegen/src/cursor.rs
View File

@@ -720,7 +720,7 @@ impl<'f> EncCursor<'f> {
///
/// This is a convenience wrapper for the DFG equivalent.
pub fn display_inst(&self, inst: ir::Inst) -> ir::dfg::DisplayInst {
self.func.dfg.display_inst(inst, self.isa)
self.func.dfg.display_inst(inst)
}
}

1
cranelift/codegen/src/ir/builder.rs
View File

@@ -7,7 +7,6 @@ use crate::ir;
use crate::ir::types;
use crate::ir::{DataFlowGraph, InstructionData};
use crate::ir::{Inst, Opcode, Type, Value};
use crate::isa;
/// Base trait for instruction builders.
///

25
cranelift/codegen/src/ir/dfg.rs
View File

@@ -10,7 +10,6 @@ use crate::ir::{
Block, FuncRef, Inst, SigRef, Signature, SourceLoc, Type, Value, ValueLabelAssignments,
ValueList, ValueListPool,
};
use crate::isa::TargetIsa;
use crate::packed_option::ReservedValue;
use crate::write::write_operands;
use crate::HashMap;
@@ -466,12 +465,8 @@ impl DataFlowGraph {
}
/// Returns an object that displays `inst`.
pub fn display_inst<'a, I: Into<Option<&'a dyn TargetIsa>>>(
&'a self,
inst: Inst,
isa: I,
) -> DisplayInst<'a> {
DisplayInst(self, isa.into(), inst)
pub fn display_inst<'a>(&'a self, inst: Inst) -> DisplayInst<'a> {
DisplayInst(self, inst)
}
/// Get all value arguments on `inst` as a slice.
@@ -657,7 +652,7 @@ impl DataFlowGraph {
old_value,
"{} wasn't detached from {}",
old_value,
self.display_inst(inst, None)
self.display_inst(inst)
);
new_value
}
@@ -963,13 +958,12 @@ impl BlockData {
}
/// Object that can display an instruction.
pub struct DisplayInst<'a>(&'a DataFlowGraph, Option<&'a dyn TargetIsa>, Inst);
pub struct DisplayInst<'a>(&'a DataFlowGraph, Inst);
impl<'a> fmt::Display for DisplayInst<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
let dfg = self.0;
let isa = self.1;
let inst = self.2;
let inst = self.1;
if let Some((first, rest)) = dfg.inst_results(inst).split_first() {
write!(f, "{}", first)?;
@@ -985,7 +979,7 @@ impl<'a> fmt::Display for DisplayInst<'a> {
} else {
write!(f, "{}.{}", dfg[inst].opcode(), typevar)?;
}
write_operands(f, dfg, isa, inst)
write_operands(f, dfg, inst)
}
}
@@ -1150,10 +1144,7 @@ mod tests {
dfg.make_inst_results(inst, types::I32);
assert_eq!(inst.to_string(), "inst0");
assert_eq!(
dfg.display_inst(inst, None).to_string(),
"v0 = iconst.i32 0"
);
assert_eq!(dfg.display_inst(inst).to_string(), "v0 = iconst.i32 0");
// Immutable reference resolution.
{
@@ -1188,7 +1179,7 @@ mod tests {
code: TrapCode::User(0),
};
let inst = dfg.make_inst(idata);
assert_eq!(dfg.display_inst(inst, None).to_string(), "trap user0");
assert_eq!(dfg.display_inst(inst).to_string(), "trap user0");
// Result slice should be empty.
assert_eq!(dfg.inst_results(inst), &[]);

111
cranelift/codegen/src/ir/extfunc.rs
View File

@@ -5,8 +5,8 @@
//!
//! This module declares the data types used to represent external functions and call signatures.
use crate::ir::{ArgumentLoc, ExternalName, SigRef, Type};
use crate::isa::{CallConv, RegInfo, RegUnit};
use crate::ir::{ExternalName, SigRef, Type};
use crate::isa::CallConv;
use crate::machinst::RelocDistance;
use alloc::vec::Vec;
use core::fmt;
@@ -50,11 +50,6 @@ impl Signature {
self.call_conv = call_conv;
}
/// Return an object that can display `self` with correct register names.
pub fn display<'a, R: Into<Option<&'a RegInfo>>>(&'a self, regs: R) -> DisplaySignature<'a> {
DisplaySignature(self, regs.into())
}
/// Find the index of a presumed unique special-purpose parameter.
pub fn special_param_index(&self, purpose: ArgumentPurpose) -> Option<usize> {
self.params.iter().rposition(|arg| arg.purpose == purpose)
@@ -108,38 +103,29 @@ impl Signature {
}
}
/// Wrapper type capable of displaying a `Signature` with correct register names.
pub struct DisplaySignature<'a>(&'a Signature, Option<&'a RegInfo>);
fn write_list(f: &mut fmt::Formatter, args: &[AbiParam], regs: Option<&RegInfo>) -> fmt::Result {
fn write_list(f: &mut fmt::Formatter, args: &[AbiParam]) -> fmt::Result {
match args.split_first() {
None => {}
Some((first, rest)) => {
write!(f, "{}", first.display(regs))?;
write!(f, "{}", first)?;
for arg in rest {
write!(f, ", {}", arg.display(regs))?;
write!(f, ", {}", arg)?;
}
}
}
Ok(())
}
impl<'a> fmt::Display for DisplaySignature<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
write!(f, "(")?;
write_list(f, &self.0.params, self.1)?;
write!(f, ")")?;
if !self.0.returns.is_empty() {
write!(f, " -> ")?;
write_list(f, &self.0.returns, self.1)?;
}
write!(f, " {}", self.0.call_conv)
}
}
impl fmt::Display for Signature {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
self.display(None).fmt(f)
write!(f, "(")?;
write_list(f, &self.params)?;
write!(f, ")")?;
if !self.returns.is_empty() {
write!(f, " -> ")?;
write_list(f, &self.returns)?;
}
write!(f, " {}", self.call_conv)
}
}
@@ -157,9 +143,6 @@ pub struct AbiParam {
/// Method for extending argument to a full register.
pub extension: ArgumentExtension,
/// ABI-specific location of this argument, or `Unassigned` for arguments that have not yet
/// been legalized.
pub location: ArgumentLoc,
/// Was the argument converted to pointer during legalization?
pub legalized_to_pointer: bool,
}
@@ -171,7 +154,6 @@ impl AbiParam {
value_type: vt,
extension: ArgumentExtension::None,
purpose: ArgumentPurpose::Normal,
location: Default::default(),
legalized_to_pointer: false,
}
}
@@ -182,18 +164,6 @@ impl AbiParam {
value_type: vt,
extension: ArgumentExtension::None,
purpose,
location: Default::default(),
legalized_to_pointer: false,
}
}
/// Create a parameter for a special-purpose register.
pub fn special_reg(vt: Type, purpose: ArgumentPurpose, regunit: RegUnit) -> Self {
Self {
value_type: vt,
extension: ArgumentExtension::None,
purpose,
location: ArgumentLoc::Reg(regunit),
legalized_to_pointer: false,
}
}
@@ -215,42 +185,23 @@ impl AbiParam {
..self
}
}
/// Return an object that can display `self` with correct register names.
pub fn display<'a, R: Into<Option<&'a RegInfo>>>(&'a self, regs: R) -> DisplayAbiParam<'a> {
DisplayAbiParam(self, regs.into())
}
}
/// Wrapper type capable of displaying a `AbiParam` with correct register names.
pub struct DisplayAbiParam<'a>(&'a AbiParam, Option<&'a RegInfo>);
impl<'a> fmt::Display for DisplayAbiParam<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
write!(f, "{}", self.0.value_type)?;
if self.0.legalized_to_pointer {
write!(f, " ptr")?;
}
match self.0.extension {
ArgumentExtension::None => {}
ArgumentExtension::Uext => write!(f, " uext")?,
ArgumentExtension::Sext => write!(f, " sext")?,
}
if self.0.purpose != ArgumentPurpose::Normal {
write!(f, " {}", self.0.purpose)?;
}
if self.0.location.is_assigned() {
write!(f, " [{}]", self.0.location.display(self.1))?;
}
Ok(())
}
}
impl fmt::Display for AbiParam {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
self.display(None).fmt(f)
write!(f, "{}", self.value_type)?;
if self.legalized_to_pointer {
write!(f, " ptr")?;
}
match self.extension {
ArgumentExtension::None => {}
ArgumentExtension::Uext => write!(f, " uext")?,
ArgumentExtension::Sext => write!(f, " sext")?,
}
if self.purpose != ArgumentPurpose::Normal {
write!(f, " {}", self.purpose)?;
}
Ok(())
}
}
@@ -519,15 +470,5 @@ mod tests {
sig.to_string(),
"(i32, i32x4) -> f32, b8 baldrdash_system_v"
);
// Order does not matter.
sig.params[0].location = ArgumentLoc::Stack(24);
sig.params[1].location = ArgumentLoc::Stack(8);
// Writing ABI-annotated signatures.
assert_eq!(
sig.to_string(),
"(i32 [24], i32x4 [8]) -> f32, b8 baldrdash_system_v"
);
}
}

36
cranelift/codegen/src/ir/function.rs
View File

@@ -10,10 +10,10 @@ use crate::ir::{
HeapData, Inst, InstructionData, JumpTable, JumpTableData, Opcode, SigRef, StackSlot,
StackSlotData, Table, TableData,
};
use crate::ir::{BlockOffsets, SourceLocs, StackSlots, ValueLocations};
use crate::ir::{BlockOffsets, SourceLocs, StackSlots};
use crate::ir::{DataFlowGraph, ExternalName, Layout, Signature};
use crate::ir::{JumpTableOffsets, JumpTables};
use crate::isa::{CallConv, TargetIsa};
use crate::isa::CallConv;
use crate::value_label::ValueLabelsRanges;
use crate::write::write_function;
#[cfg(feature = "enable-serde")]
@@ -104,9 +104,6 @@ pub struct Function {
/// Layout of blocks and instructions in the function body.
pub layout: Layout,
/// Location assigned to every value.
pub locations: ValueLocations,
/// Code offsets of the block headers.
///
/// This information is only transiently available after the `binemit::relax_branches` function
@@ -156,7 +153,6 @@ impl Function {
jump_tables: PrimaryMap::new(),
dfg: DataFlowGraph::new(),
layout: Layout::new(),
locations: SecondaryMap::new(),
offsets: SecondaryMap::new(),
jt_offsets: SecondaryMap::new(),
srclocs: SecondaryMap::new(),
@@ -176,7 +172,6 @@ impl Function {
self.jump_tables.clear();
self.dfg.clear();
self.layout.clear();
self.locations.clear();
self.offsets.clear();
self.jt_offsets.clear();
self.srclocs.clear();
@@ -227,11 +222,8 @@ impl Function {
}
/// Return an object that can display this function with correct ISA-specific annotations.
pub fn display<'a, I: Into<Option<&'a dyn TargetIsa>>>(
&'a self,
isa: I,
) -> DisplayFunction<'a> {
DisplayFunction(self, isa.into().into())
pub fn display(&self) -> DisplayFunction<'_> {
DisplayFunction(self, Default::default())
}
/// Return an object that can display this function with correct ISA-specific annotations.
@@ -295,7 +287,7 @@ impl Function {
}
_ => panic!(
"Unexpected instruction {} having default destination",
self.dfg.display_inst(inst, None)
self.dfg.display_inst(inst)
),
}
}
@@ -372,39 +364,27 @@ impl Function {
/// Additional annotations for function display.
#[derive(Default)]
pub struct DisplayFunctionAnnotations<'a> {
/// Enable ISA annotations.
pub isa: Option<&'a dyn TargetIsa>,
/// Enable value labels annotations.
pub value_ranges: Option<&'a ValueLabelsRanges>,
}
impl<'a> From<Option<&'a dyn TargetIsa>> for DisplayFunctionAnnotations<'a> {
fn from(isa: Option<&'a dyn TargetIsa>) -> DisplayFunctionAnnotations {
DisplayFunctionAnnotations {
isa,
value_ranges: None,
}
}
}
/// Wrapper type capable of displaying a `Function` with correct ISA annotations.
pub struct DisplayFunction<'a>(&'a Function, DisplayFunctionAnnotations<'a>);
impl<'a> fmt::Display for DisplayFunction<'a> {
fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
write_function(fmt, self.0, &self.1)
write_function(fmt, self.0)
}
}
impl fmt::Display for Function {
fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
write_function(fmt, self, &DisplayFunctionAnnotations::default())
write_function(fmt, self)
}
}
impl fmt::Debug for Function {
fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
write_function(fmt, self, &DisplayFunctionAnnotations::default())
write_function(fmt, self)
}
}

1
cranelift/codegen/src/ir/instructions.rs
View File

@@ -25,7 +25,6 @@ use crate::ir::{
trapcode::TrapCode,
types, Block, FuncRef, JumpTable, MemFlags, SigRef, StackSlot, Type, Value,
};
use crate::isa;
/// Some instructions use an external list of argument values because there is not enough space in
/// the 16-byte `InstructionData` struct. These value lists are stored in a memory pool in

46
cranelift/codegen/src/ir/libcall.rs
View File

@@ -1,10 +1,6 @@
//! Naming well-known routines in the runtime library.
use crate::ir::{
types, AbiParam, ArgumentPurpose, ExtFuncData, ExternalName, FuncRef, Function, Opcode,
Signature, Type,
};
use crate::isa::{CallConv, RegUnit, TargetIsa};
use crate::ir::{types, ExternalName, FuncRef, Function, Opcode, Type};
use core::fmt;
use core::str::FromStr;
#[cfg(feature = "enable-serde")]
@@ -169,14 +165,8 @@ impl LibCall {
/// Get a function reference for the probestack function in `func`.
///
/// If there is an existing reference, use it, otherwise make a new one.
pub fn get_probestack_funcref(
func: &mut Function,
reg_type: Type,
arg_reg: RegUnit,
isa: &dyn TargetIsa,
) -> FuncRef {
pub fn get_probestack_funcref(func: &mut Function) -> Option<FuncRef> {
find_funcref(LibCall::Probestack, func)
.unwrap_or_else(|| make_funcref_for_probestack(func, reg_type, arg_reg, isa))
}
/// Get the existing function reference for `libcall` in `func` if it exists.
@@ -196,38 +186,6 @@ fn find_funcref(libcall: LibCall, func: &Function) -> Option<FuncRef> {
None
}
/// Create a funcref for `LibCall::Probestack`.
fn make_funcref_for_probestack(
func: &mut Function,
reg_type: Type,
arg_reg: RegUnit,
isa: &dyn TargetIsa,
) -> FuncRef {
let mut sig = Signature::new(CallConv::Probestack);
let rax = AbiParam::special_reg(reg_type, ArgumentPurpose::Normal, arg_reg);
sig.params.push(rax);
if !isa.flags().probestack_func_adjusts_sp() {
sig.returns.push(rax);
}
make_funcref(LibCall::Probestack, func, sig, isa)
}
/// Create a funcref for `libcall`.
fn make_funcref(
libcall: LibCall,
func: &mut Function,
sig: Signature,
isa: &dyn TargetIsa,
) -> FuncRef {
let sigref = func.import_signature(sig);
func.import_function(ExtFuncData {
name: ExternalName::LibCall(libcall),
signature: sigref,
colocated: isa.flags().use_colocated_libcalls(),
})
}
#[cfg(test)]
mod tests {
use super::*;

5
cranelift/codegen/src/ir/mod.rs
View File

@@ -22,7 +22,6 @@ pub mod stackslot;
mod table;
mod trapcode;
pub mod types;
mod valueloc;
#[cfg(feature = "enable-serde")]
use serde::{Deserialize, Serialize};
@@ -57,16 +56,12 @@ pub use crate::ir::stackslot::{StackLayoutInfo, StackSlotData, StackSlotKind, St
pub use crate::ir::table::TableData;
pub use crate::ir::trapcode::TrapCode;
pub use crate::ir::types::Type;
pub use crate::ir::valueloc::{ArgumentLoc, ValueLoc};
pub use crate::value_label::LabelValueLoc;
pub use cranelift_codegen_shared::condcodes;
use crate::binemit;
use crate::entity::{entity_impl, PrimaryMap, SecondaryMap};
/// Map of value locations.
pub type ValueLocations = SecondaryMap<Value, ValueLoc>;
/// Map of jump tables.
pub type JumpTables = PrimaryMap<JumpTable, JumpTableData>;

166
cranelift/codegen/src/ir/valueloc.rs
View File

@@ -1,166 +0,0 @@
//! Value locations.
//!
//! The register allocator assigns every SSA value to either a register or a stack slot. This
//! assignment is represented by a `ValueLoc` object.
use crate::ir::StackSlot;
use crate::isa::{RegInfo, RegUnit};
use core::fmt;
#[cfg(feature = "enable-serde")]
use serde::{Deserialize, Serialize};
/// Value location.
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
pub enum ValueLoc {
/// This value has not been assigned to a location yet.
Unassigned,
/// Value is assigned to a register.
Reg(RegUnit),
/// Value is assigned to a stack slot.
Stack(StackSlot),
}
impl Default for ValueLoc {
fn default() -> Self {
Self::Unassigned
}
}
impl ValueLoc {
/// Is this an assigned location? (That is, not `Unassigned`).
pub fn is_assigned(self) -> bool {
match self {
Self::Unassigned => false,
_ => true,
}
}
/// Get the register unit of this location, or panic.
pub fn unwrap_reg(self) -> RegUnit {
match self {
Self::Reg(ru) => ru,
_ => panic!("unwrap_reg expected register, found {:?}", self),
}
}
/// Get the stack slot of this location, or panic.
pub fn unwrap_stack(self) -> StackSlot {
match self {
Self::Stack(ss) => ss,
_ => panic!("unwrap_stack expected stack slot, found {:?}", self),
}
}
/// Return an object that can display this value location, using the register info from the
/// target ISA.
pub fn display<'a, R: Into<Option<&'a RegInfo>>>(self, regs: R) -> DisplayValueLoc<'a> {
DisplayValueLoc(self, regs.into())
}
}
/// Displaying a `ValueLoc` correctly requires the associated `RegInfo` from the target ISA.
/// Without the register info, register units are simply show as numbers.
///
/// The `DisplayValueLoc` type can display the contained `ValueLoc`.
pub struct DisplayValueLoc<'a>(ValueLoc, Option<&'a RegInfo>);
impl<'a> fmt::Display for DisplayValueLoc<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self.0 {
ValueLoc::Unassigned => write!(f, "-"),
ValueLoc::Reg(ru) => match self.1 {
Some(regs) => write!(f, "{}", regs.display_regunit(ru)),
None => write!(f, "%{}", ru),
},
ValueLoc::Stack(ss) => write!(f, "{}", ss),
}
}
}
/// Function argument location.
///
/// The ABI specifies how arguments are passed to a function, and where return values appear after
/// the call. Just like a `ValueLoc`, function arguments can be passed in registers or on the
/// stack.
///
/// Function arguments on the stack are accessed differently for the incoming arguments to the
/// current function and the outgoing arguments to a called external function. For this reason,
/// the location of stack arguments is described as an offset into the array of function arguments
/// on the stack.
///
/// An `ArgumentLoc` can be translated to a `ValueLoc` only when we know if we're talking about an
/// incoming argument or an outgoing argument.
///
/// - For stack arguments, different `StackSlot` entities are used to represent incoming and
/// outgoing arguments.
/// - For register arguments, there is usually no difference, but if we ever add support for a
/// register-window ISA like SPARC, register arguments would also need to be translated.
#[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)]
#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
pub enum ArgumentLoc {
/// This argument has not been assigned to a location yet.
Unassigned,
/// Argument is passed in a register.
Reg(RegUnit),
/// Argument is passed on the stack, at the given byte offset into the argument array.
Stack(i32),
}
impl Default for ArgumentLoc {
fn default() -> Self {
Self::Unassigned
}
}
impl ArgumentLoc {
/// Is this an assigned location? (That is, not `Unassigned`).
pub fn is_assigned(self) -> bool {
match self {
Self::Unassigned => false,
_ => true,
}
}
/// Is this a register location?
pub fn is_reg(self) -> bool {
match self {
Self::Reg(_) => true,
_ => false,
}
}
/// Is this a stack location?
pub fn is_stack(self) -> bool {
match self {
Self::Stack(_) => true,
_ => false,
}
}
/// Return an object that can display this argument location, using the register info from the
/// target ISA.
pub fn display<'a, R: Into<Option<&'a RegInfo>>>(self, regs: R) -> DisplayArgumentLoc<'a> {
DisplayArgumentLoc(self, regs.into())
}
}
/// Displaying a `ArgumentLoc` correctly requires the associated `RegInfo` from the target ISA.
/// Without the register info, register units are simply show as numbers.
///
/// The `DisplayArgumentLoc` type can display the contained `ArgumentLoc`.
pub struct DisplayArgumentLoc<'a>(ArgumentLoc, Option<&'a RegInfo>);
impl<'a> fmt::Display for DisplayArgumentLoc<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self.0 {
ArgumentLoc::Unassigned => write!(f, "-"),
ArgumentLoc::Reg(ru) => match self.1 {
Some(regs) => write!(f, "{}", regs.display_regunit(ru)),
None => write!(f, "%{}", ru),
},
ArgumentLoc::Stack(offset) => write!(f, "{}", offset),
}
}
}

2
cranelift/codegen/src/isa/aarch64/lower.rs
View File

@@ -1407,7 +1407,7 @@ pub(crate) fn lower_i64x2_mul<C: LowerCtx<I = Inst>>(c: &mut C, insn: IRInst) {
// rd = |dg+ch|be+af||dg+ch|be+af|
c.emit(Inst::VecRRR {
alu_op: VecALUOp::Addp,
rd: rd,
rd,
rn: rd.to_reg(),
rm: rd.to_reg(),
size: VectorSize::Size32x4,

25
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -482,9 +482,9 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
ctx.emit(Inst::AluRRRR {
alu_op: ALUOp3::MSub64,
rd: rd,
rd,
rn: rd.to_reg(),
rm: rm,
rm,
ra: rn,
});
} else {
@@ -2165,16 +2165,11 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
Opcode::Spill
| Opcode::Fill
| Opcode::FillNop
| Opcode::Regmove
| Opcode::CopySpecial
| Opcode::CopyToSsa
| Opcode::CopyNop
| Opcode::AdjustSpDown
| Opcode::AdjustSpUpImm
| Opcode::AdjustSpDownImm
| Opcode::IfcmpSp
| Opcode::Regspill
| Opcode::Regfill => {
| Opcode::IfcmpSp => {
panic!("Unused opcode should not be encountered.");
}
@@ -2412,7 +2407,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
alu_op: VecALUOp::Umaxp,
rd: tmp,
rn: rm,
rm: rm,
rm,
size,
});
} else {
@@ -2835,9 +2830,9 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
ctx.emit(Inst::VecRRR {
alu_op: VecALUOp::Addp,
rd: rd,
rn: rn,
rm: rm,
rd,
rn,
rm,
size: VectorSize::from_ty(ty),
});
}
@@ -3446,7 +3441,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
ctx.emit(Inst::FpuRRR {
fpu_op: choose_32_64(in_ty, FPUOp2::Min32, FPUOp2::Min64),
rd: rtmp2,
rn: rn,
rn,
rm: rtmp1.to_reg(),
});
if in_bits == 32 {
@@ -3468,7 +3463,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
}
if in_bits == 32 {
ctx.emit(Inst::FpuCmp32 { rn: rn, rm: rn });
ctx.emit(Inst::FpuCmp32 { rn, rm: rn });
ctx.emit(Inst::FpuCSel32 {
rd: rtmp2,
rn: rtmp1.to_reg(),
@@ -3476,7 +3471,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
cond: Cond::Ne,
});
} else {
ctx.emit(Inst::FpuCmp64 { rn: rn, rm: rn });
ctx.emit(Inst::FpuCmp64 { rn, rm: rn });
ctx.emit(Inst::FpuCSel64 {
rd: rtmp2,
rn: rtmp1.to_reg(),

13
cranelift/codegen/src/isa/aarch64/mod.rs
View File

@@ -11,7 +11,6 @@ use crate::machinst::{
use crate::result::CodegenResult;
use crate::settings as shared_settings;
use alloc::{boxed::Box, vec::Vec};
use core::hash::{Hash, Hasher};
use regalloc::{PrettyPrint, RealRegUniverse};
use target_lexicon::{Aarch64Architecture, Architecture, Triple};
@@ -111,11 +110,6 @@ impl MachBackend for AArch64Backend {
self.isa_flags.iter().collect()
}
fn hash_all_flags(&self, mut hasher: &mut dyn Hasher) {
self.flags.hash(&mut hasher);
self.isa_flags.hash(&mut hasher);
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
@@ -126,13 +120,6 @@ impl MachBackend for AArch64Backend {
IntCC::UnsignedGreaterThanOrEqual
}
fn unsigned_sub_overflow_condition(&self) -> IntCC {
// unsigned `<`; this corresponds to the carry flag cleared on aarch64, which happens on
// underflow of a subtract (aarch64 follows a carry-cleared-on-borrow convention, the
// opposite of x86).
IntCC::UnsignedLessThan
}
#[cfg(feature = "unwind")]
fn emit_unwind_info(
&self,

10
cranelift/codegen/src/isa/arm32/mod.rs
View File

@@ -11,7 +11,6 @@ use crate::result::CodegenResult;
use crate::settings;
use alloc::{boxed::Box, vec::Vec};
use core::hash::{Hash, Hasher};
use regalloc::{PrettyPrint, RealRegUniverse};
use target_lexicon::{Architecture, ArmArchitecture, Triple};
@@ -101,10 +100,6 @@ impl MachBackend for Arm32Backend {
Vec::new()
}
fn hash_all_flags(&self, mut hasher: &mut dyn Hasher) {
self.flags.hash(&mut hasher);
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
@@ -114,11 +109,6 @@ impl MachBackend for Arm32Backend {
IntCC::UnsignedGreaterThanOrEqual
}
fn unsigned_sub_overflow_condition(&self) -> IntCC {
// Carry flag clear.
IntCC::UnsignedLessThan
}
fn text_section_builder(&self, num_funcs: u32) -> Box<dyn TextSectionBuilder> {
Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
}

77
cranelift/codegen/src/isa/constraints.rs
View File

@@ -8,83 +8,6 @@
//! are satisfied.
use crate::binemit::CodeOffset;
use crate::ir::ValueLoc;
use crate::isa::{RegClass, RegUnit};
/// Register constraint for a single value operand or instruction result.
#[derive(PartialEq, Debug)]
pub struct OperandConstraint {
/// The kind of constraint.
pub kind: ConstraintKind,
/// The register class of the operand.
///
/// This applies to all kinds of constraints, but with slightly different meaning.
pub regclass: RegClass,
}
impl OperandConstraint {
/// Check if this operand constraint is satisfied by the given value location.
/// For tied constraints, this only checks the register class, not that the
/// counterpart operand has the same value location.
pub fn satisfied(&self, loc: ValueLoc) -> bool {
match self.kind {
ConstraintKind::Reg | ConstraintKind::Tied(_) => {
if let ValueLoc::Reg(reg) = loc {
self.regclass.contains(reg)
} else {
false
}
}
ConstraintKind::FixedReg(reg) | ConstraintKind::FixedTied(reg) => {
loc == ValueLoc::Reg(reg) && self.regclass.contains(reg)
}
ConstraintKind::Stack => {
if let ValueLoc::Stack(_) = loc {
true
} else {
false
}
}
}
}
}
/// The different kinds of operand constraints.
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum ConstraintKind {
/// This operand or result must be a register from the given register class.
Reg,
/// This operand or result must be a fixed register.
///
/// The constraint's `regclass` field is the top-level register class containing the fixed
/// register.
FixedReg(RegUnit),
/// This result value must use the same register as an input value operand.
///
/// The associated number is the index of the input value operand this result is tied to. The
/// constraint's `regclass` field is the same as the tied operand's register class.
///
/// When an (in, out) operand pair is tied, this constraint kind appears in both the `ins` and
/// the `outs` arrays. The constraint for the in operand is `Tied(out)`, and the constraint for
/// the out operand is `Tied(in)`.
Tied(u8),
/// This operand must be a fixed register, and it has a tied counterpart.
///
/// This works just like `FixedReg`, but additionally indicates that there are identical
/// input/output operands for this fixed register. For an input operand, this means that the
/// value will be clobbered by the instruction
FixedTied(RegUnit),
/// This operand must be a value in a stack slot.
///
/// The constraint's `regclass` field is the register class that would normally be used to load
/// and store values of this type.
Stack,
}
/// Constraints on the range of a branch instruction.
///

178
cranelift/codegen/src/isa/mod.rs
View File

@@ -44,8 +44,7 @@
//! concurrent function compilations.
pub use crate::isa::call_conv::CallConv;
pub use crate::isa::constraints::{BranchRange, ConstraintKind, OperandConstraint};
pub use crate::isa::registers::{regs_overlap, RegClass, RegClassIndex, RegInfo, RegUnit};
pub use crate::isa::constraints::BranchRange;
pub use crate::isa::stack::{StackBase, StackBaseMask, StackRef};
use crate::flowgraph;
@@ -57,10 +56,8 @@ use crate::result::CodegenResult;
use crate::settings;
use crate::settings::SetResult;
use alloc::{boxed::Box, vec::Vec};
use core::any::Any;
use core::fmt;
use core::fmt::{Debug, Formatter};
use core::hash::Hasher;
use target_lexicon::{triple, Architecture, OperatingSystem, PointerWidth, Triple};
// This module is made public here for benchmarking purposes. No guarantees are
@@ -81,7 +78,6 @@ pub mod unwind;
mod call_conv;
mod constraints;
pub mod registers;
mod stack;
#[cfg(test)]
@@ -220,8 +216,9 @@ impl TargetFrontendConfig {
}
}
/// Methods that are specialized to a target ISA. Implies a Display trait that shows the
/// shared flags, as well as any isa-specific flags.
/// Methods that are specialized to a target ISA.
///
/// Implies a Display trait that shows the shared flags, as well as any ISA-specific flags.
pub trait TargetIsa: fmt::Display + Send + Sync {
/// Get the name of this ISA.
fn name(&self) -> &'static str;
@@ -235,85 +232,6 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
/// Get the ISA-dependent flag values that were used to make this trait object.
fn isa_flags(&self) -> Vec<settings::Value>;
/// Hashes all flags, both ISA-independent and ISA-specific, into the
/// specified hasher.
fn hash_all_flags(&self, hasher: &mut dyn Hasher);
/// Get the default calling convention of this target.
fn default_call_conv(&self) -> CallConv {
CallConv::triple_default(self.triple())
}
/// Get the endianness of this ISA.
fn endianness(&self) -> ir::Endianness {
match self.triple().endianness().unwrap() {
target_lexicon::Endianness::Little => ir::Endianness::Little,
target_lexicon::Endianness::Big => ir::Endianness::Big,
}
}
/// Returns the code (text) section alignment for this ISA.
fn code_section_alignment(&self) -> u64 {
use target_lexicon::*;
match (self.triple().operating_system, self.triple().architecture) {
(
OperatingSystem::MacOSX { .. }
| OperatingSystem::Darwin
| OperatingSystem::Ios
| OperatingSystem::Tvos,
Architecture::Aarch64(..),
) => 0x4000,
_ => 0x1000,
}
}
/// Get the pointer type of this ISA.
fn pointer_type(&self) -> ir::Type {
ir::Type::int(u16::from(self.pointer_bits())).unwrap()
}
/// Get the width of pointers on this ISA.
fn pointer_width(&self) -> PointerWidth {
self.triple().pointer_width().unwrap()
}
/// Get the width of pointers on this ISA, in units of bits.
fn pointer_bits(&self) -> u8 {
self.pointer_width().bits()
}
/// Get the width of pointers on this ISA, in units of bytes.
fn pointer_bytes(&self) -> u8 {
self.pointer_width().bytes()
}
/// Get the information needed by frontends producing Cranelift IR.
fn frontend_config(&self) -> TargetFrontendConfig {
TargetFrontendConfig {
default_call_conv: self.default_call_conv(),
pointer_width: self.pointer_width(),
}
}
/// Does the CPU implement scalar comparisons using a CPU flags register?
fn uses_cpu_flags(&self) -> bool {
false
}
/// Does the CPU implement multi-register addressing?
fn uses_complex_addresses(&self) -> bool {
false
}
/// Get a data structure describing the registers in this ISA.
fn register_info(&self) -> RegInfo;
#[cfg(feature = "unwind")]
/// Map a Cranelift register to its corresponding DWARF register.
fn map_dwarf_register(&self, _: RegUnit) -> Result<u16, RegisterMappingError> {
Err(RegisterMappingError::UnsupportedArchitecture)
}
#[cfg(feature = "unwind")]
/// Map a regalloc::Reg to its corresponding DWARF register.
fn map_regalloc_reg_to_dwarf(&self, _: ::regalloc::Reg) -> Result<u16, RegisterMappingError> {
@@ -323,21 +241,6 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
/// IntCC condition for Unsigned Addition Overflow (Carry).
fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC;
/// IntCC condition for Unsigned Subtraction Overflow (Borrow/Carry).
fn unsigned_sub_overflow_condition(&self) -> ir::condcodes::IntCC;
/// Returns the flavor of unwind information emitted for this target.
fn unwind_info_kind(&self) -> UnwindInfoKind {
match self.triple().operating_system {
#[cfg(feature = "unwind")]
OperatingSystem::Windows => UnwindInfoKind::Windows,
#[cfg(feature = "unwind")]
_ => UnwindInfoKind::SystemV,
#[cfg(not(feature = "unwind"))]
_ => UnwindInfoKind::None,
}
}
/// Creates unwind information for the function.
///
/// Returns `None` if there is no unwind information for the function.
@@ -363,10 +266,77 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
fn get_mach_backend(&self) -> Option<&dyn MachBackend> {
None
}
}
/// Return an [Any] reference for downcasting to the ISA-specific implementation of this trait
/// with `isa.as_any().downcast_ref::<isa::foo::Isa>()`.
fn as_any(&self) -> &dyn Any;
/// Methods implemented for free for target ISA!
impl<'a> dyn TargetIsa + 'a {
/// Get the default calling convention of this target.
pub fn default_call_conv(&self) -> CallConv {
CallConv::triple_default(self.triple())
}
/// Get the endianness of this ISA.
pub fn endianness(&self) -> ir::Endianness {
match self.triple().endianness().unwrap() {
target_lexicon::Endianness::Little => ir::Endianness::Little,
target_lexicon::Endianness::Big => ir::Endianness::Big,
}
}
/// Returns the code (text) section alignment for this ISA.
pub fn code_section_alignment(&self) -> u64 {
use target_lexicon::*;
match (self.triple().operating_system, self.triple().architecture) {
(
OperatingSystem::MacOSX { .. }
| OperatingSystem::Darwin
| OperatingSystem::Ios
| OperatingSystem::Tvos,
Architecture::Aarch64(..),
) => 0x4000,
_ => 0x1000,
}
}
/// Get the pointer type of this ISA.
pub fn pointer_type(&self) -> ir::Type {
ir::Type::int(u16::from(self.pointer_bits())).unwrap()
}
/// Get the width of pointers on this ISA.
pub(crate) fn pointer_width(&self) -> PointerWidth {
self.triple().pointer_width().unwrap()
}
/// Get the width of pointers on this ISA, in units of bits.
pub fn pointer_bits(&self) -> u8 {
self.pointer_width().bits()
}
/// Get the width of pointers on this ISA, in units of bytes.
pub fn pointer_bytes(&self) -> u8 {
self.pointer_width().bytes()
}
/// Get the information needed by frontends producing Cranelift IR.
pub fn frontend_config(&self) -> TargetFrontendConfig {
TargetFrontendConfig {
default_call_conv: self.default_call_conv(),
pointer_width: self.pointer_width(),
}
}
/// Returns the flavor of unwind information emitted for this target.
pub(crate) fn unwind_info_kind(&self) -> UnwindInfoKind {
match self.triple().operating_system {
#[cfg(feature = "unwind")]
OperatingSystem::Windows => UnwindInfoKind::Windows,
#[cfg(feature = "unwind")]
_ => UnwindInfoKind::SystemV,
#[cfg(not(feature = "unwind"))]
_ => UnwindInfoKind::None,
}
}
}
impl Debug for &dyn TargetIsa {

360
cranelift/codegen/src/isa/registers.rs
View File

@@ -1,360 +0,0 @@
//! Data structures describing the registers in an ISA.
use crate::entity::EntityRef;
use core::fmt;
/// Register units are the smallest units of register allocation.
///
/// Normally there is a 1-1 correspondence between registers and register units, but when an ISA
/// has aliasing registers, the aliasing can be modeled with registers that cover multiple
/// register units.
///
/// The register allocator will enforce that each register unit only gets used for one thing.
pub type RegUnit = u16;
/// A bit mask indexed by register classes.
///
/// The size of this type is determined by the ISA with the most register classes.
pub type RegClassMask = u32;
/// A bit mask indexed by register units.
///
/// The size of this type is determined by the target ISA that has the most register units defined.
/// Currently that is arm32 which has 64+16 units.
pub type RegUnitMask = [RegClassMask; 3];
/// The register units in a target ISA are divided into disjoint register banks. Each bank covers a
/// contiguous range of register units.
///
/// The `RegBank` struct provides a static description of a register bank.
pub struct RegBank {
/// The name of this register bank as defined in the ISA's DSL definition.
pub name: &'static str,
/// The first register unit in this bank.
pub first_unit: RegUnit,
/// The total number of register units in this bank.
pub units: RegUnit,
/// Array of specially named register units. This array can be shorter than the number of units
/// in the bank.
pub names: &'static [&'static str],
/// Name prefix to use for those register units in the bank not covered by the `names` array.
/// The remaining register units will be named this prefix followed by their decimal offset in
/// the bank. So with a prefix `r`, registers will be named `r8`, `r9`, ...
pub prefix: &'static str,
/// Index of the first top-level register class in this bank.
pub first_toprc: usize,
/// Number of top-level register classes in this bank.
///
/// The top-level register classes in a bank are guaranteed to be numbered sequentially from
/// `first_toprc`, and all top-level register classes across banks come before any sub-classes.
pub num_toprcs: usize,
/// Is register pressure tracking enabled for this bank?
pub pressure_tracking: bool,
}
impl RegBank {
/// Does this bank contain `regunit`?
fn contains(&self, regunit: RegUnit) -> bool {
regunit >= self.first_unit && regunit - self.first_unit < self.units
}
/// Try to parse a regunit name. The name is not expected to begin with `%`.
fn parse_regunit(&self, name: &str) -> Option<RegUnit> {
match self.names.iter().position(|&x| x == name) {
Some(offset) => {
// This is one of the special-cased names.
Some(offset as RegUnit)
}
None => {
// Try a regular prefixed name.
if name.starts_with(self.prefix) {
name[self.prefix.len()..].parse().ok()
} else {
None
}
}
}
.and_then(|offset| {
if offset < self.units {
Some(offset + self.first_unit)
} else {
None
}
})
}
/// Write `regunit` to `w`, assuming that it belongs to this bank.
/// All regunits are written with a `%` prefix.
fn write_regunit(&self, f: &mut fmt::Formatter, regunit: RegUnit) -> fmt::Result {
let offset = regunit - self.first_unit;
assert!(offset < self.units);
if (offset as usize) < self.names.len() {
write!(f, "%{}", self.names[offset as usize])
} else {
write!(f, "%{}{}", self.prefix, offset)
}
}
}
/// A register class reference.
///
/// All register classes are statically defined in tables generated from the meta descriptions.
pub type RegClass = &'static RegClassData;
/// Data about a register class.
///
/// A register class represents a subset of the registers in a bank. It describes the set of
/// permitted registers for a register operand in a given encoding of an instruction.
///
/// A register class can be a subset of another register class. The top-level register classes are
/// disjoint.
pub struct RegClassData {
/// The name of the register class.
pub name: &'static str,
/// The index of this class in the ISA's RegInfo description.
pub index: u8,
/// How many register units to allocate per register.
pub width: u8,
/// Index of the register bank this class belongs to.
pub bank: u8,
/// Index of the top-level register class contains this one.
pub toprc: u8,
/// The first register unit in this class.
pub first: RegUnit,
/// Bit-mask of sub-classes of this register class, including itself.
///
/// Bits correspond to RC indexes.
pub subclasses: RegClassMask,
/// Mask of register units in the class. If `width > 1`, the mask only has a bit set for the
/// first register unit in each allocatable register.
pub mask: RegUnitMask,
/// The global `RegInfo` instance containing this register class.
pub info: &'static RegInfo,
/// The "pinned" register of the associated register bank.
///
/// This register must be non-volatile (callee-preserved) and must not be the fixed
/// output register of any instruction.
pub pinned_reg: Option<RegUnit>,
}
impl RegClassData {
/// Get the register class index corresponding to the intersection of `self` and `other`.
///
/// This register class is guaranteed to exist if the register classes overlap. If the register
/// classes don't overlap, returns `None`.
pub fn intersect_index(&self, other: RegClass) -> Option<RegClassIndex> {
// Compute the set of common subclasses.
let mask = self.subclasses & other.subclasses;
if mask == 0 {
// No overlap.
None
} else {
// Register class indexes are topologically ordered, so the largest common subclass has
// the smallest index.
Some(RegClassIndex(mask.trailing_zeros() as u8))
}
}
/// Get the intersection of `self` and `other`.
pub fn intersect(&self, other: RegClass) -> Option<RegClass> {
self.intersect_index(other).map(|rci| self.info.rc(rci))
}
/// Returns true if `other` is a subclass of this register class.
/// A register class is considered to be a subclass of itself.
pub fn has_subclass<RCI: Into<RegClassIndex>>(&self, other: RCI) -> bool {
self.subclasses & (1 << other.into().0) as u32 != 0
}
/// Get the top-level register class containing this class.
pub fn toprc(&self) -> RegClass {
self.info.rc(RegClassIndex(self.toprc))
}
/// Get a specific register unit in this class.
pub fn unit(&self, offset: usize) -> RegUnit {
let uoffset = offset * usize::from(self.width);
self.first + uoffset as RegUnit
}
/// Does this register class contain `regunit`?
pub fn contains(&self, regunit: RegUnit) -> bool {
self.mask[(regunit / 32) as usize] & (1u32 << (regunit % 32) as u32) != 0
}
/// If the pinned register is used, is the given regunit the pinned register of this class?
#[inline]
pub fn is_pinned_reg(&self, enabled: bool, regunit: RegUnit) -> bool {
enabled
&& self
.pinned_reg
.map_or(false, |pinned_reg| pinned_reg == regunit)
}
/// Calculate the index of the register inside the class.
pub fn index_of(&self, regunit: RegUnit) -> u16 {
assert!(
self.contains(regunit),
"the {} register class does not contain {}",
self.name,
regunit
);
regunit - self.first
}
}
impl fmt::Display for RegClassData {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.write_str(self.name)
}
}
impl fmt::Debug for RegClassData {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.write_str(self.name)
}
}
/// Within an ISA, register classes are uniquely identified by their index.
impl PartialEq for RegClassData {
fn eq(&self, other: &Self) -> bool {
self.index == other.index
}
}
/// A small reference to a register class.
///
/// Use this when storing register classes in compact data structures. The `RegInfo::rc()` method
/// can be used to get the real register class reference back.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct RegClassIndex(u8);
impl EntityRef for RegClassIndex {
fn new(idx: usize) -> Self {
Self(idx as u8)
}
fn index(self) -> usize {
usize::from(self.0)
}
}
impl From<RegClass> for RegClassIndex {
fn from(rc: RegClass) -> Self {
Self(rc.index)
}
}
impl fmt::Display for RegClassIndex {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
write!(f, "rci{}", self.0)
}
}
/// Test of two registers overlap.
///
/// A register is identified as a `(RegClass, RegUnit)` pair. The register class is needed to
/// determine the width (in regunits) of the register.
pub fn regs_overlap(rc1: RegClass, reg1: RegUnit, rc2: RegClass, reg2: RegUnit) -> bool {
let end1 = reg1 + RegUnit::from(rc1.width);
let end2 = reg2 + RegUnit::from(rc2.width);
!(end1 <= reg2 || end2 <= reg1)
}
/// Information about the registers in an ISA.
///
/// The `RegUnit` data structure collects all relevant static information about the registers in an
/// ISA.
#[derive(Clone)]
pub struct RegInfo {
/// All register banks, ordered by their `first_unit`. The register banks are disjoint, but
/// there may be holes of unused register unit numbers between banks due to alignment.
pub banks: &'static [RegBank],
/// All register classes ordered topologically so a sub-class always follows its parent.
pub classes: &'static [RegClass],
}
impl RegInfo {
/// Get the register bank holding `regunit`.
pub fn bank_containing_regunit(&self, regunit: RegUnit) -> Option<&RegBank> {
// We could do a binary search, but most ISAs have only two register banks...
self.banks.iter().find(|b| b.contains(regunit))
}
/// Try to parse a regunit name. The name is not expected to begin with `%`.
pub fn parse_regunit(&self, name: &str) -> Option<RegUnit> {
self.banks
.iter()
.filter_map(|b| b.parse_regunit(name))
.next()
}
/// Make a temporary object that can display a register unit.
pub fn display_regunit(&self, regunit: RegUnit) -> DisplayRegUnit {
DisplayRegUnit {
regunit,
reginfo: self,
}
}
/// Get the register class corresponding to `idx`.
pub fn rc(&self, idx: RegClassIndex) -> RegClass {
self.classes[idx.index()]
}
/// Get the top-level register class containing the `idx` class.
pub fn toprc(&self, idx: RegClassIndex) -> RegClass {
self.classes[self.rc(idx).toprc as usize]
}
}
/// Temporary object that holds enough information to print a register unit.
pub struct DisplayRegUnit<'a> {
regunit: RegUnit,
reginfo: &'a RegInfo,
}
impl<'a> fmt::Display for DisplayRegUnit<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self.reginfo.bank_containing_regunit(self.regunit) {
Some(b) => b.write_regunit(f, self.regunit),
None => write!(f, "%INVALID{}", self.regunit),
}
}
}
#[test]
fn assert_sizes() {
use cranelift_codegen_shared::constants;
use std::mem::size_of;
// In these tests, size_of returns number of bytes: we actually want the number of bits, so
// multiply these by 8.
assert!(
(size_of::<RegClassMask>() * 8) <= constants::MAX_NUM_REG_CLASSES,
"need to bump MAX_NUM_REG_CLASSES or change RegClassMask type"
);
assert!(
constants::MAX_NUM_REG_CLASSES < (1 << (size_of::<RegClassIndex>() * 8)),
"need to change RegClassIndex's type to a wider type"
);
}

31
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -661,16 +661,7 @@ fn lower_icmp_to_flags<C: LowerCtx<I = Inst>>(
(false, true) => NarrowValueMode::SignExtend64,
(false, false) => NarrowValueMode::ZeroExtend64,
};
let inputs = [
InsnInput {
insn: insn,
input: 0,
},
InsnInput {
insn: insn,
input: 1,
},
];
let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
let ty = ctx.input_ty(insn, 0);
let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
if is_signed {
@@ -759,16 +750,7 @@ fn lower_icmp_to_flags<C: LowerCtx<I = Inst>>(
fn lower_fcmp_to_flags<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
let ty = ctx.input_ty(insn, 0);
let bits = ty_bits(ty);
let inputs = [
InsnInput {
insn: insn,
input: 0,
},
InsnInput {
insn: insn,
input: 1,
},
];
let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
match bits {
@@ -2909,17 +2891,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
Opcode::Spill
| Opcode::Fill
| Opcode::FillNop
| Opcode::Regmove
| Opcode::CopySpecial
| Opcode::CopyToSsa
| Opcode::CopyNop
| Opcode::AdjustSpDown
| Opcode::AdjustSpUpImm
| Opcode::AdjustSpDownImm
| Opcode::DummySargT
| Opcode::IfcmpSp
| Opcode::Regspill
| Opcode::Regfill => {
| Opcode::IfcmpSp => {
panic!("Unused opcode should not be encountered.");
}
@@ -3117,7 +3094,7 @@ fn lower_branch<C: LowerCtx<I = Inst>>(
info: Box::new(JTSequenceInfo {
default_target,
targets: jt_targets,
targets_for_term: targets_for_term,
targets_for_term,
}),
});
}

10
cranelift/codegen/src/isa/s390x/mod.rs
View File

@@ -14,7 +14,6 @@ use crate::result::CodegenResult;
use crate::settings as shared_settings;
use alloc::{boxed::Box, vec::Vec};
use core::hash::{Hash, Hasher};
use regalloc::{PrettyPrint, RealRegUniverse, Reg};
use target_lexicon::{Architecture, Triple};
@@ -114,11 +113,6 @@ impl MachBackend for S390xBackend {
self.isa_flags.iter().collect()
}
fn hash_all_flags(&self, mut hasher: &mut dyn Hasher) {
self.flags.hash(&mut hasher);
self.isa_flags.hash(&mut hasher);
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
@@ -132,10 +126,6 @@ impl MachBackend for S390xBackend {
IntCC::UnsignedGreaterThan
}
fn unsigned_sub_overflow_condition(&self) -> IntCC {
unimplemented!()
}
#[cfg(feature = "unwind")]
fn emit_unwind_info(
&self,

6
cranelift/codegen/src/isa/test_utils.rs
View File

@@ -2,9 +2,7 @@
#![allow(dead_code)]
use crate::binemit::{Addend, CodeOffset, CodeSink, Reloc};
use crate::ir::Value;
use crate::ir::{ConstantOffset, ExternalName, Function, JumpTable, Opcode, SourceLoc, TrapCode};
use crate::isa::TargetIsa;
use crate::ir::{ConstantOffset, ExternalName, JumpTable, Opcode, SourceLoc, TrapCode};
use alloc::vec::Vec;
use std::string::String;
@@ -80,7 +78,5 @@ impl CodeSink for TestCodeSink {
fn end_codegen(&mut self) {}
fn add_stack_map(&mut self, _val_list: &[Value], _func: &Function, _isa: &dyn TargetIsa) {}
fn add_call_site(&mut self, _opcode: Opcode, _srcloc: SourceLoc) {}
}

5
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -6865,16 +6865,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
Opcode::Spill
| Opcode::Fill
| Opcode::FillNop
| Opcode::Regmove
| Opcode::CopySpecial
| Opcode::CopyToSsa
| Opcode::CopyNop
| Opcode::AdjustSpDown
| Opcode::AdjustSpUpImm
| Opcode::AdjustSpDownImm
| Opcode::IfcmpSp
| Opcode::Regspill
| Opcode::Regfill
| Opcode::Copy
| Opcode::DummySargT => {
panic!("Unused opcode should not be encountered.");

12
cranelift/codegen/src/isa/x64/mod.rs
View File

@@ -15,7 +15,6 @@ use crate::machinst::{
use crate::result::CodegenResult;
use crate::settings::{self as shared_settings, Flags};
use alloc::{boxed::Box, vec::Vec};
use core::hash::{Hash, Hasher};
use regalloc::{PrettyPrint, RealRegUniverse, Reg};
use target_lexicon::Triple;
@@ -95,11 +94,6 @@ impl MachBackend for X64Backend {
self.x64_flags.iter().collect()
}
fn hash_all_flags(&self, mut hasher: &mut dyn Hasher) {
self.flags.hash(&mut hasher);
self.x64_flags.hash(&mut hasher);
}
fn name(&self) -> &'static str {
"x64"
}
@@ -118,12 +112,6 @@ impl MachBackend for X64Backend {
IntCC::UnsignedLessThan
}
fn unsigned_sub_overflow_condition(&self) -> IntCC {
// unsigned `<`; this corresponds to the carry flag set on x86, which
// indicates a sub has underflowed (carry is borrow for subtract).
IntCC::UnsignedLessThan
}
#[cfg(feature = "unwind")]
fn emit_unwind_info(
&self,

2
cranelift/codegen/src/legalizer/globalvalue.rs
View File

@@ -24,7 +24,7 @@ pub fn expand_global_value(
debug_assert_eq!(opcode, ir::Opcode::GlobalValue);
global_value
}
_ => panic!("Wanted global_value: {}", func.dfg.display_inst(inst, None)),
_ => panic!("Wanted global_value: {}", func.dfg.display_inst(inst)),
};
match func.global_values[gv] {

2
cranelift/codegen/src/legalizer/heap.rs
View File

@@ -27,7 +27,7 @@ pub fn expand_heap_addr(
debug_assert_eq!(opcode, ir::Opcode::HeapAddr);
(heap, arg, u64::from(imm))
}
_ => panic!("Wanted heap_addr: {}", func.dfg.display_inst(inst, None)),
_ => panic!("Wanted heap_addr: {}", func.dfg.display_inst(inst)),
};
match func.heaps[heap].style {

30
cranelift/codegen/src/legalizer/mod.rs
View File

@@ -40,7 +40,7 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
} => (arg, imm),
_ => panic!(
concat!("Expected ", stringify!($from), ": {}"),
$pos.func.dfg.display_inst($inst, None)
$pos.func.dfg.display_inst($inst)
),
};
let ty = $pos.func.dfg.value_type(arg);
@@ -57,7 +57,7 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
} => (arg, imm),
_ => panic!(
concat!("Expected ", stringify!($from), ": {}"),
$pos.func.dfg.display_inst($inst, None)
$pos.func.dfg.display_inst($inst)
),
};
let imm = $pos.ins().iconst($ty, imm);
@@ -106,10 +106,7 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
arg,
imm,
} => (arg, imm),
_ => panic!(
"Expected irsub_imm: {}",
pos.func.dfg.display_inst(inst, None)
),
_ => panic!("Expected irsub_imm: {}", pos.func.dfg.display_inst(inst)),
};
let ty = pos.func.dfg.value_type(arg);
let imm = pos.ins().iconst(ty, imm);
@@ -131,10 +128,7 @@ pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa:
arg,
imm,
} => (cond, arg, imm),
_ => panic!(
"Expected ircmp_imm: {}",
pos.func.dfg.display_inst(inst, None)
),
_ => panic!("Expected ircmp_imm: {}", pos.func.dfg.display_inst(inst)),
};
let ty = pos.func.dfg.value_type(x);
let y = pos.ins().iconst(ty, y);
@@ -170,11 +164,11 @@ fn expand_cond_trap(
trapz = match opcode {
ir::Opcode::Trapz => true,
ir::Opcode::Trapnz | ir::Opcode::ResumableTrapnz => false,
_ => panic!("Expected cond trap: {}", func.dfg.display_inst(inst, None)),
_ => panic!("Expected cond trap: {}", func.dfg.display_inst(inst)),
};
(arg, code, opcode)
}
_ => panic!("Expected cond trap: {}", func.dfg.display_inst(inst, None)),
_ => panic!("Expected cond trap: {}", func.dfg.display_inst(inst)),
};
// Split the block after `inst`:
@@ -250,7 +244,7 @@ fn expand_br_icmp(
destination,
args.as_slice(&func.dfg.value_lists)[2..].to_vec(),
),
_ => panic!("Expected br_icmp {}", func.dfg.display_inst(inst, None)),
_ => panic!("Expected br_icmp {}", func.dfg.display_inst(inst)),
};
let old_block = func.layout.pp_block(inst);
@@ -284,10 +278,7 @@ fn expand_stack_load(
stack_slot,
offset,
} => (stack_slot, offset),
_ => panic!(
"Expected stack_load: {}",
pos.func.dfg.display_inst(inst, None)
),
_ => panic!("Expected stack_load: {}", pos.func.dfg.display_inst(inst)),
};
let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);
@@ -316,10 +307,7 @@ fn expand_stack_store(
stack_slot,
offset,
} => (arg, stack_slot, offset),
_ => panic!(
"Expected stack_store: {}",
pos.func.dfg.display_inst(inst, None)
),
_ => panic!("Expected stack_store: {}", pos.func.dfg.display_inst(inst)),
};
let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);

2
cranelift/codegen/src/legalizer/table.rs
View File

@@ -28,7 +28,7 @@ pub fn expand_table_addr(
debug_assert_eq!(opcode, ir::Opcode::TableAddr);
(table, arg, offset)
}
_ => panic!("Wanted table_addr: {}", func.dfg.display_inst(inst, None)),
_ => panic!("Wanted table_addr: {}", func.dfg.display_inst(inst)),
};
dynamic_addr(inst, table, index, element_offset, func);

23
cranelift/codegen/src/machinst/adapter.rs
View File

@@ -1,14 +1,13 @@
//! Adapter for a `MachBackend` to implement the `TargetIsa` trait.
use crate::ir;
use crate::isa::{RegInfo, TargetIsa};
use crate::isa::TargetIsa;
use crate::machinst::*;
use crate::settings::{self, Flags};
#[cfg(feature = "unwind")]
use crate::isa::unwind::systemv::RegisterMappingError;
use core::any::Any;
use std::fmt;
use target_lexicon::Triple;
@@ -56,18 +55,6 @@ impl TargetIsa for TargetIsaAdapter {
self.backend.isa_flags()
}
fn hash_all_flags(&self, hasher: &mut dyn Hasher) {
self.backend.hash_all_flags(hasher);
}
fn register_info(&self) -> RegInfo {
// Called from function's Display impl, so we need a stub here.
RegInfo {
banks: &[],
classes: &[],
}
}
fn get_mach_backend(&self) -> Option<&dyn MachBackend> {
Some(&*self.backend)
}
@@ -76,10 +63,6 @@ impl TargetIsa for TargetIsaAdapter {
self.backend.unsigned_add_overflow_condition()
}
fn unsigned_sub_overflow_condition(&self) -> ir::condcodes::IntCC {
self.backend.unsigned_sub_overflow_condition()
}
#[cfg(feature = "unwind")]
fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
self.backend.create_systemv_cie()
@@ -89,8 +72,4 @@ impl TargetIsa for TargetIsaAdapter {
fn map_regalloc_reg_to_dwarf(&self, r: Reg) -> Result<u16, RegisterMappingError> {
self.backend.map_reg_to_dwarf(r)
}
fn as_any(&self) -> &dyn Any {
self as &dyn Any
}
}

4
cranelift/codegen/src/machinst/buffer.rs
View File

@@ -1641,10 +1641,9 @@ impl<I: VCodeInst> TextSectionBuilder for MachTextSectionBuilder<I> {
#[cfg(all(test, feature = "arm64"))]
mod test {
use super::*;
use crate::ir::{ConstantOffset, Function, JumpTable, Value};
use crate::ir::{ConstantOffset, JumpTable};
use crate::isa::aarch64::inst::xreg;
use crate::isa::aarch64::inst::{BranchTarget, CondBrKind, EmitInfo, Inst};
use crate::isa::TargetIsa;
use crate::machinst::MachInstEmit;
use crate::settings;
use std::default::Default;
@@ -2076,7 +2075,6 @@ mod test {
fn begin_jumptables(&mut self) {}
fn begin_rodata(&mut self) {}
fn end_codegen(&mut self) {}
fn add_stack_map(&mut self, _: &[Value], _: &Function, _: &dyn TargetIsa) {}
fn add_call_site(&mut self, op: Opcode, _: SourceLoc) {
self.callsites.push((self.offset, op));
}

8
cranelift/codegen/src/machinst/mod.rs
View File

@@ -69,7 +69,6 @@ use crate::value_label::ValueLabelsRanges;
use alloc::boxed::Box;
use alloc::vec::Vec;
use core::fmt::Debug;
use core::hash::Hasher;
use cranelift_entity::PrimaryMap;
use regalloc::RegUsageCollector;
use regalloc::{
@@ -389,9 +388,6 @@ pub trait MachBackend {
/// Get the ISA-dependent flag values that were used to make this trait object.
fn isa_flags(&self) -> Vec<settings::Value>;
/// Hashes all flags, both ISA-independent and ISA-dependent, into the specified hasher.
fn hash_all_flags(&self, hasher: &mut dyn Hasher);
/// Return triple for this backend.
fn triple(&self) -> Triple;
@@ -405,10 +401,6 @@ pub trait MachBackend {
/// Condition that will be true when an IaddIfcout overflows.
fn unsigned_add_overflow_condition(&self) -> IntCC;
/// Machine-specific condcode info needed by TargetIsa.
/// Condition that will be true when an IsubIfcout overflows.
fn unsigned_sub_overflow_condition(&self) -> IntCC;
/// Produces unwind info based on backend results.
#[cfg(feature = "unwind")]
fn emit_unwind_info(

19
cranelift/codegen/src/print_errors.rs
View File

@@ -4,7 +4,6 @@ use crate::entity::SecondaryMap;
use crate::ir;
use crate::ir::entities::{AnyEntity, Block, Inst, Value};
use crate::ir::function::Function;
use crate::isa::TargetIsa;
use crate::result::CodegenError;
use crate::verifier::{VerifierError, VerifierErrors};
use crate::write::{decorate_function, FuncWriter, PlainWriter};
@@ -17,7 +16,6 @@ use core::fmt::Write;
/// Pretty-print a verifier error.
pub fn pretty_verifier_error<'a>(
func: &ir::Function,
isa: Option<&dyn TargetIsa>,
func_w: Option<Box<dyn FuncWriter + 'a>>,
errors: VerifierErrors,
) -> String {
@@ -29,7 +27,6 @@ pub fn pretty_verifier_error<'a>(
&mut PrettyVerifierError(func_w.unwrap_or_else(|| Box::new(PlainWriter)), &mut errors),
&mut w,
func,
&isa.into(),
)
.unwrap();
@@ -51,11 +48,10 @@ impl<'a> FuncWriter for PrettyVerifierError<'a> {
&mut self,
w: &mut dyn Write,
func: &Function,
isa: Option<&dyn TargetIsa>,
block: Block,
indent: usize,
) -> fmt::Result {
pretty_block_header_error(w, func, isa, block, indent, &mut *self.0, self.1)
pretty_block_header_error(w, func, block, indent, &mut *self.0, self.1)
}
fn write_instruction(
@@ -63,11 +59,10 @@ impl<'a> FuncWriter for PrettyVerifierError<'a> {
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
isa: Option<&dyn TargetIsa>,
inst: Inst,
indent: usize,
) -> fmt::Result {
pretty_instruction_error(w, func, aliases, isa, inst, indent, &mut *self.0, self.1)
pretty_instruction_error(w, func, aliases, inst, indent, &mut *self.0, self.1)
}
fn write_entity_definition(
@@ -85,14 +80,13 @@ impl<'a> FuncWriter for PrettyVerifierError<'a> {
fn pretty_block_header_error(
w: &mut dyn Write,
func: &Function,
isa: Option<&dyn TargetIsa>,
cur_block: Block,
indent: usize,
func_w: &mut dyn FuncWriter,
errors: &mut Vec<VerifierError>,
) -> fmt::Result {
let mut s = String::new();
func_w.write_block_header(&mut s, func, isa, cur_block, indent)?;
func_w.write_block_header(&mut s, func, cur_block, indent)?;
write!(w, "{}", s)?;
// TODO: Use drain_filter here when it gets stabilized
@@ -124,14 +118,13 @@ fn pretty_instruction_error(
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
isa: Option<&dyn TargetIsa>,
cur_inst: Inst,
indent: usize,
func_w: &mut dyn FuncWriter,
errors: &mut Vec<VerifierError>,
) -> fmt::Result {
let mut s = String::new();
func_w.write_instruction(&mut s, func, aliases, isa, cur_inst, indent)?;
func_w.write_instruction(&mut s, func, aliases, cur_inst, indent)?;
write!(w, "{}", s)?;
// TODO: Use drain_filter here when it gets stabilized
@@ -218,9 +211,9 @@ fn print_error(w: &mut dyn Write, err: VerifierError) -> fmt::Result {
}
/// Pretty-print a Cranelift error.
pub fn pretty_error(func: &ir::Function, isa: Option<&dyn TargetIsa>, err: CodegenError) -> String {
pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String {
if let CodegenError::Verifier(e) = err {
pretty_verifier_error(func, isa, None, e)
pretty_verifier_error(func, None, e)
} else {
err.to_string()
}

2
cranelift/codegen/src/unreachable_code.rs
View File

@@ -31,7 +31,7 @@ pub fn eliminate_unreachable_code(
// Remove all instructions from `block`.
while let Some(inst) = pos.func.layout.first_inst(block) {
log::trace!(" - {}", pos.func.dfg.display_inst(inst, None));
log::trace!(" - {}", pos.func.dfg.display_inst(inst));
pos.func.layout.remove_inst(inst);
}

109
cranelift/codegen/src/verifier/mod.rs
View File

@@ -65,9 +65,8 @@ use crate::ir;
use crate::ir::entities::AnyEntity;
use crate::ir::instructions::{BranchInfo, CallInfo, InstructionFormat, ResolvedConstraint};
use crate::ir::{
types, ArgumentLoc, ArgumentPurpose, Block, Constant, FuncRef, Function, GlobalValue, Inst,
InstructionData, JumpTable, Opcode, SigRef, StackSlot, StackSlotKind, Type, Value, ValueDef,
ValueList, ValueLoc,
types, ArgumentPurpose, Block, Constant, FuncRef, Function, GlobalValue, Inst, InstructionData,
JumpTable, Opcode, SigRef, StackSlot, Type, Value, ValueDef, ValueList,
};
use crate::isa::TargetIsa;
use crate::iterators::IteratorExtras;
@@ -319,7 +318,7 @@ impl<'a> Verifier<'a> {
/// Determine a contextual error string for an instruction.
#[inline]
fn context(&self, inst: Inst) -> String {
self.func.dfg.display_inst(inst, self.isa).to_string()
self.func.dfg.display_inst(inst).to_string()
}
// Check for:
@@ -700,12 +699,6 @@ impl<'a> Verifier<'a> {
TableAddr { table, .. } => {
self.verify_table(inst, table, errors)?;
}
RegSpill { dst, .. } => {
self.verify_stack_slot(inst, dst, errors)?;
}
RegFill { src, .. } => {
self.verify_stack_slot(inst, src, errors)?;
}
LoadComplex { ref args, .. } => {
self.verify_value_list(inst, args, errors)?;
}
@@ -775,9 +768,6 @@ impl<'a> Verifier<'a> {
| IntSelect { .. }
| Load { .. }
| Store { .. }
| RegMove { .. }
| CopySpecial { .. }
| CopyToSsa { .. }
| Trap { .. }
| CondTrap { .. }
| IntCondTrap { .. }
@@ -1377,7 +1367,6 @@ impl<'a> Verifier<'a> {
.iter()
.map(|a| a.value_type);
self.typecheck_variable_args_iterator(inst, arg_types, errors)?;
self.check_outgoing_args(inst, sig_ref, errors)?;
}
CallInfo::Indirect(sig_ref, _) => {
let arg_types = self.func.dfg.signatures[sig_ref]
@@ -1385,7 +1374,6 @@ impl<'a> Verifier<'a> {
.iter()
.map(|a| a.value_type);
self.typecheck_variable_args_iterator(inst, arg_types, errors)?;
self.check_outgoing_args(inst, sig_ref, errors)?;
}
CallInfo::NotACall => {}
}
@@ -1427,7 +1415,7 @@ impl<'a> Verifier<'a> {
self.context(inst),
format!(
"mismatched argument count for `{}`: got {}, expected {}",
self.func.dfg.display_inst(inst, None),
self.func.dfg.display_inst(inst),
variable_args.len(),
i,
),
@@ -1436,77 +1424,6 @@ impl<'a> Verifier<'a> {
Ok(())
}
/// Check the locations assigned to outgoing call arguments.
///
/// When a signature has been legalized, all values passed as outgoing arguments on the stack
/// must be assigned to a matching `OutgoingArg` stack slot.
fn check_outgoing_args(
&self,
inst: Inst,
sig_ref: SigRef,
errors: &mut VerifierErrors,
) -> VerifierStepResult<()> {
let sig = &self.func.dfg.signatures[sig_ref];
let args = self.func.dfg.inst_variable_args(inst);
let expected_args = &sig.params[..];
for (&arg, &abi) in args.iter().zip(expected_args) {
// Value types have already been checked by `typecheck_variable_args_iterator()`.
if let ArgumentLoc::Stack(offset) = abi.location {
let arg_loc = self.func.locations[arg];
if let ValueLoc::Stack(ss) = arg_loc {
// Argument value is assigned to a stack slot as expected.
self.verify_stack_slot(inst, ss, errors)?;
let slot = &self.func.stack_slots[ss];
if slot.kind != StackSlotKind::OutgoingArg {
return errors.fatal((
inst,
self.context(inst),
format!(
"Outgoing stack argument {} in wrong stack slot: {} = {}",
arg, ss, slot,
),
));
}
if slot.offset != Some(offset) {
return errors.fatal((
inst,
self.context(inst),
format!(
"Outgoing stack argument {} should have offset {}: {} = {}",
arg, offset, ss, slot,
),
));
}
if abi.purpose == ArgumentPurpose::StructArgument(slot.size) {
} else if slot.size != abi.value_type.bytes() {
return errors.fatal((
inst,
self.context(inst),
format!(
"Outgoing stack argument {} wrong size for {}: {} = {}",
arg, abi.value_type, ss, slot,
),
));
}
} else {
let reginfo = self.isa.map(|i| i.register_info());
return errors.fatal((
inst,
self.context(inst),
format!(
"Outgoing stack argument {} in wrong location: {}",
arg,
arg_loc.display(reginfo.as_ref())
),
));
}
}
}
Ok(())
}
fn typecheck_return(&self, inst: Inst, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
if self.func.dfg[inst].opcode().is_return() {
let args = self.func.dfg.inst_variable_args(inst);
@@ -1668,22 +1585,6 @@ impl<'a> Verifier<'a> {
"copy_nop src and dst types must be the same",
));
}
let src_loc = self.func.locations[arg];
let dst_loc = self.func.locations[dst_val];
let locs_ok = match (src_loc, dst_loc) {
(ValueLoc::Stack(src_slot), ValueLoc::Stack(dst_slot)) => src_slot == dst_slot,
_ => false,
};
if !locs_ok {
return errors.fatal((
inst,
self.context(inst),
format!(
"copy_nop must refer to identical stack slots, but found {:?} vs {:?}",
src_loc, dst_loc,
),
));
}
}
Ok(())
}
@@ -1903,7 +1804,7 @@ impl<'a> Verifier<'a> {
if !errors.is_empty() {
log::warn!(
"Found verifier errors in function:\n{}",
pretty_verifier_error(self.func, None, None, errors.clone())
pretty_verifier_error(self.func, None, errors.clone())
);
}

143
cranelift/codegen/src/write.rs
View File

@@ -5,10 +5,7 @@
use crate::entity::SecondaryMap;
use crate::ir::entities::AnyEntity;
use crate::ir::{
Block, DataFlowGraph, DisplayFunctionAnnotations, Function, Inst, SigRef, Type, Value, ValueDef,
};
use crate::isa::{RegInfo, TargetIsa};
use crate::ir::{Block, DataFlowGraph, Function, Inst, SigRef, Type, Value, ValueDef};
use crate::packed_option::ReservedValue;
use alloc::string::String;
use alloc::vec::Vec;
@@ -21,7 +18,6 @@ pub trait FuncWriter {
&mut self,
w: &mut dyn Write,
func: &Function,
isa: Option<&dyn TargetIsa>,
block: Block,
indent: usize,
) -> fmt::Result;
@@ -32,28 +28,17 @@ pub trait FuncWriter {
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
isa: Option<&dyn TargetIsa>,
inst: Inst,
indent: usize,
) -> fmt::Result;
/// Write the preamble to `w`. By default, this uses `write_entity_definition`.
fn write_preamble(
&mut self,
w: &mut dyn Write,
func: &Function,
regs: Option<&RegInfo>,
) -> Result<bool, fmt::Error> {
self.super_preamble(w, func, regs)
fn write_preamble(&mut self, w: &mut dyn Write, func: &Function) -> Result<bool, fmt::Error> {
self.super_preamble(w, func)
}
/// Default impl of `write_preamble`
fn super_preamble(
&mut self,
w: &mut dyn Write,
func: &Function,
regs: Option<&RegInfo>,
) -> Result<bool, fmt::Error> {
fn super_preamble(&mut self, w: &mut dyn Write, func: &Function) -> Result<bool, fmt::Error> {
let mut any = false;
for (ss, slot) in func.stack_slots.iter() {
@@ -84,7 +69,7 @@ pub trait FuncWriter {
// signatures.
for (sig, sig_data) in &func.dfg.signatures {
any = true;
self.write_entity_definition(w, func, sig.into(), &sig_data.display(regs))?;
self.write_entity_definition(w, func, sig.into(), &sig_data)?;
}
for (fnref, ext_func) in &func.dfg.ext_funcs {
@@ -145,33 +130,27 @@ impl FuncWriter for PlainWriter {
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
isa: Option<&dyn TargetIsa>,
inst: Inst,
indent: usize,
) -> fmt::Result {
write_instruction(w, func, aliases, isa, inst, indent)
write_instruction(w, func, aliases, inst, indent)
}
fn write_block_header(
&mut self,
w: &mut dyn Write,
func: &Function,
isa: Option<&dyn TargetIsa>,
block: Block,
indent: usize,
) -> fmt::Result {
write_block_header(w, func, isa, block, indent)
write_block_header(w, func, block, indent)
}
}
/// Write `func` to `w` as equivalent text.
/// Use `isa` to emit ISA-dependent annotations.
pub fn write_function(
w: &mut dyn Write,
func: &Function,
annotations: &DisplayFunctionAnnotations,
) -> fmt::Result {
decorate_function(&mut PlainWriter, w, func, annotations)
pub fn write_function(w: &mut dyn Write, func: &Function) -> fmt::Result {
decorate_function(&mut PlainWriter, w, func)
}
/// Create a reverse-alias map from a value to all aliases having that value as a direct target
@@ -193,21 +172,17 @@ pub fn decorate_function<FW: FuncWriter>(
func_w: &mut FW,
w: &mut dyn Write,
func: &Function,
annotations: &DisplayFunctionAnnotations,
) -> fmt::Result {
let regs = annotations.isa.map(TargetIsa::register_info);
let regs = regs.as_ref();
write!(w, "function ")?;
write_spec(w, func, regs)?;
write_spec(w, func)?;
writeln!(w, " {{")?;
let aliases = alias_map(func);
let mut any = func_w.write_preamble(w, func, regs)?;
let mut any = func_w.write_preamble(w, func)?;
for block in &func.layout {
if any {
writeln!(w)?;
}
decorate_block(func_w, w, func, &aliases, annotations, block)?;
decorate_block(func_w, w, func, &aliases, block)?;
any = true;
}
writeln!(w, "}}")
@@ -217,27 +192,16 @@ pub fn decorate_function<FW: FuncWriter>(
//
// Function spec.
fn write_spec(w: &mut dyn Write, func: &Function, regs: Option<&RegInfo>) -> fmt::Result {
write!(w, "{}{}", func.name, func.signature.display(regs))
fn write_spec(w: &mut dyn Write, func: &Function) -> fmt::Result {
write!(w, "{}{}", func.name, func.signature)
}
//----------------------------------------------------------------------
//
// Basic blocks
fn write_arg(
w: &mut dyn Write,
func: &Function,
regs: Option<&RegInfo>,
arg: Value,
) -> fmt::Result {
write!(w, "{}: {}", arg, func.dfg.value_type(arg))?;
let loc = func.locations[arg];
if loc.is_assigned() {
write!(w, " [{}]", loc.display(regs))?
}
Ok(())
fn write_arg(w: &mut dyn Write, func: &Function, arg: Value) -> fmt::Result {
write!(w, "{}: {}", arg, func.dfg.value_type(arg))
}
/// Write out the basic block header, outdented:
@@ -249,28 +213,24 @@ fn write_arg(
pub fn write_block_header(
w: &mut dyn Write,
func: &Function,
isa: Option<&dyn TargetIsa>,
block: Block,
indent: usize,
) -> fmt::Result {
// The `indent` is the instruction indentation. block headers are 4 spaces out from that.
write!(w, "{1:0$}{2}", indent - 4, "", block)?;
let regs = isa.map(TargetIsa::register_info);
let regs = regs.as_ref();
let mut args = func.dfg.block_params(block).iter().cloned();
match args.next() {
None => return writeln!(w, ":"),
Some(arg) => {
write!(w, "(")?;
write_arg(w, func, regs, arg)?;
write_arg(w, func, arg)?;
}
}
// Remaining arguments.
for arg in args {
write!(w, ", ")?;
write_arg(w, func, regs, arg)?;
write_arg(w, func, arg)?;
}
writeln!(w, "):")
}
@@ -280,20 +240,18 @@ fn decorate_block<FW: FuncWriter>(
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
annotations: &DisplayFunctionAnnotations,
block: Block,
) -> fmt::Result {
// Indent all instructions if any srclocs are present.
let indent = if func.srclocs.is_empty() { 4 } else { 36 };
let isa = annotations.isa;
func_w.write_block_header(w, func, isa, block, indent)?;
func_w.write_block_header(w, func, block, indent)?;
for a in func.dfg.block_params(block).iter().cloned() {
write_value_aliases(w, aliases, a, indent)?;
}
for inst in func.layout.block_insts(block) {
func_w.write_instruction(w, func, aliases, isa, inst, indent)?;
func_w.write_instruction(w, func, aliases, inst, indent)?;
}
Ok(())
@@ -359,7 +317,6 @@ fn write_instruction(
w: &mut dyn Write,
func: &Function,
aliases: &SecondaryMap<Value, Vec<Value>>,
isa: Option<&dyn TargetIsa>,
inst: Inst,
indent: usize,
) -> fmt::Result {
@@ -397,7 +354,7 @@ fn write_instruction(
None => write!(w, "{}", opcode)?,
}
write_operands(w, &func.dfg, isa, inst)?;
write_operands(w, &func.dfg, inst)?;
writeln!(w)?;
// Value aliases come out on lines after the instruction defining the referent.
@@ -408,12 +365,7 @@ fn write_instruction(
}
/// Write the operands of `inst` to `w` with a prepended space.
pub fn write_operands(
w: &mut dyn Write,
dfg: &DataFlowGraph,
isa: Option<&dyn TargetIsa>,
inst: Inst,
) -> fmt::Result {
pub fn write_operands(w: &mut dyn Write, dfg: &DataFlowGraph, inst: Inst) -> fmt::Result {
let pool = &dfg.value_lists;
use crate::ir::instructions::InstructionData::*;
match dfg[inst] {
@@ -582,57 +534,6 @@ pub fn write_operands(
offset
)
}
RegMove { arg, src, dst, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
write!(
w,
" {}, {} -> {}",
arg,
regs.display_regunit(src),
regs.display_regunit(dst)
)
} else {
write!(w, " {}, %{} -> %{}", arg, src, dst)
}
}
CopySpecial { src, dst, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
write!(
w,
" {} -> {}",
regs.display_regunit(src),
regs.display_regunit(dst)
)
} else {
write!(w, " %{} -> %{}", src, dst)
}
}
CopyToSsa { src, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
write!(w, " {}", regs.display_regunit(src))
} else {
write!(w, " %{}", src)
}
}
RegSpill { arg, src, dst, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
write!(w, " {}, {} -> {}", arg, regs.display_regunit(src), dst)
} else {
write!(w, " {}, %{} -> {}", arg, src, dst)
}
}
RegFill { arg, src, dst, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
write!(w, " {}, {} -> {}", arg, src, regs.display_regunit(dst))
} else {
write!(w, " {}, {} -> %{}", arg, src, dst)
}
}
Trap { code, .. } => write!(w, " {}", code),
CondTrap { arg, code, .. } => write!(w, " {}, {}", arg, code),
IntCondTrap {