Remove more old backend ISA concepts (#3402)
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate. Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
This commit is contained in:
Benjamin Bouvier
@@ -1954,65 +1954,6 @@ pub(crate) fn define(
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.operands_out(vec![sarg_t]),
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);
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let src = &Operand::new("src", &imm.regunit);
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let dst = &Operand::new("dst", &imm.regunit);
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ig.push(
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Inst::new(
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"regmove",
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r#"
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Temporarily divert ``x`` from ``src`` to ``dst``.
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This instruction moves the location of a value from one register to
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another without creating a new SSA value. It is used by the register
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allocator to temporarily rearrange register assignments in order to
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satisfy instruction constraints.
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The register diversions created by this instruction must be undone
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before the value leaves the block. At the entry to a new block, all live
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values must be in their originally assigned registers.
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"#,
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&formats.reg_move,
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)
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.operands_in(vec![x, src, dst])
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.other_side_effects(true),
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);
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ig.push(
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Inst::new(
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"copy_special",
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r#"
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Copies the contents of ''src'' register to ''dst'' register.
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This instructions copies the contents of one register to another
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register without involving any SSA values. This is used for copying
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special registers, e.g. copying the stack register to the frame
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register in a function prologue.
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"#,
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&formats.copy_special,
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)
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.operands_in(vec![src, dst])
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.other_side_effects(true),
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);
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ig.push(
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Inst::new(
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"copy_to_ssa",
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r#"
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Copies the contents of ''src'' register to ''a'' SSA name.
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This instruction copies the contents of one register, regardless of its SSA name, to
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another register, creating a new SSA name. In that sense it is a one-sided version
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of ''copy_special''. This instruction is internal and should not be created by
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Cranelift users.
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"#,
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&formats.copy_to_ssa,
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)
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.operands_in(vec![src])
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.operands_out(vec![a])
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.other_side_effects(true),
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);
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ig.push(
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Inst::new(
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"copy_nop",
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@@ -2098,44 +2039,6 @@ pub(crate) fn define(
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.operands_out(vec![f]),
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);
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ig.push(
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Inst::new(
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"regspill",
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r#"
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Temporarily divert ``x`` from ``src`` to ``SS``.
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This instruction moves the location of a value from a register to a
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stack slot without creating a new SSA value. It is used by the register
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allocator to temporarily rearrange register assignments in order to
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satisfy instruction constraints.
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See also `regmove`.
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"#,
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&formats.reg_spill,
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)
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.operands_in(vec![x, src, SS])
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.other_side_effects(true),
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);
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ig.push(
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Inst::new(
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"regfill",
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r#"
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Temporarily divert ``x`` from ``SS`` to ``dst``.
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This instruction moves the location of a value from a stack slot to a
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register without creating a new SSA value. It is used by the register
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allocator to temporarily rearrange register assignments in order to
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satisfy instruction constraints.
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See also `regmove`.
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"#,
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&formats.reg_fill,
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)
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.operands_in(vec![x, SS, dst])
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.other_side_effects(true),
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);
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let N =
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&Operand::new("args", &entities.varargs).with_doc("Variable number of args for StackMap");
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@@ -2302,10 +2205,9 @@ pub(crate) fn define(
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| of | * | Overflow |
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| nof | * | No Overflow |
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\* The unsigned version of overflow conditions have ISA-specific
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semantics and thus have been kept as methods on the TargetIsa trait as
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[unsigned_add_overflow_condition][isa::TargetIsa::unsigned_add_overflow_condition] and
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[unsigned_sub_overflow_condition][isa::TargetIsa::unsigned_sub_overflow_condition].
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\* The unsigned version of overflow condition for add has ISA-specific semantics and thus
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has been kept as a method on the TargetIsa trait as
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[unsigned_add_overflow_condition][crate::isa::TargetIsa::unsigned_add_overflow_condition].
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When this instruction compares integer vectors, it returns a boolean
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vector of lane-wise comparisons.
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