riscv64: Support non 128bit vector sizes (#6266)

* riscv64: Add `Zvl` extensions

* riscv64: Allow lowering SIMD operations that fit in a vector register

* riscv64: Support non 128bit vector sizes

* riscv64: Add Zvl Presets

* riscv64: Precompute `min_vec_reg_size`

cranelift/filetests/filetests/isa/riscv64/simd-iadd-big.clif

@@ -0,0 +1,40 @@
+test compile precise-output
+set unwind_info=false
+target riscv64 has_v has_zvl2048b
+
+
+
+function %iadd_i64x4(i64x4, i64x4) -> i64x4 {
+block0(v0:i64x4, v1:i64x4):
+    v2 = iadd v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   vadd.vv v10,v11,v10 #avl=4, #vtype=(e64, m1, ta, ma)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x82, 0xcd
+;   .byte 0x57, 0x05, 0xb5, 0x02
+;   ret
+
+function %iadd_i64x8(i64x8, i64x8) -> i64x8 {
+block0(v0:i64x8, v1:i64x8):
+    v2 = iadd v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   vadd.vv v10,v11,v10 #avl=8, #vtype=(e64, m1, ta, ma)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x84, 0xcd
+;   .byte 0x57, 0x05, 0xb5, 0x02
+;   ret
+

cranelift/filetests/filetests/isa/riscv64/simd-iadd-small.clif

@@ -0,0 +1,56 @@
+test compile precise-output
+set unwind_info=false
+target riscv64 has_v
+
+
+function %iadd_i8x8(i8x8, i8x8) -> i8x8 {
+block0(v0:i8x8, v1:i8x8):
+    v2 = iadd v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   vadd.vv v10,v11,v10 #avl=8, #vtype=(e8, m1, ta, ma)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x04, 0xcc
+;   .byte 0x57, 0x05, 0xb5, 0x02
+;   ret
+
+function %iadd_i16x4(i16x4, i16x4) -> i16x4 {
+block0(v0:i16x4, v1:i16x4):
+    v2 = iadd v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   vadd.vv v10,v11,v10 #avl=4, #vtype=(e16, m1, ta, ma)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x82, 0xcc
+;   .byte 0x57, 0x05, 0xb5, 0x02
+;   ret
+
+function %iadd_i32x2(i32x2, i32x2) -> i32x2 {
+block0(v0:i32x2, v1:i32x2):
+    v2 = iadd v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   vadd.vv v10,v11,v10 #avl=2, #vtype=(e32, m1, ta, ma)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x01, 0xcd
+;   .byte 0x57, 0x05, 0xb5, 0x02
+;   ret
+

cranelift/filetests/filetests/runtests/simd-iadd-small.clif

@@ -0,0 +1,31 @@
+test interpret
+test run
+target riscv64 has_v
+
+;; We only test 64bit values here since the interpreter does not support anything smaller.
+
+function %iadd_i8x8(i8x8, i8x8) -> i8x8 {
+block0(v0:i8x8, v1:i8x8):
+    v2 = iadd v0, v1
+    return v2
+}
+; run: %iadd_i8x8([1 1 1 1 1 1 1 1], [1 2 3 4 5 6 7 8]) == [2 3 4 5 6 7 8 9]
+; run: %iadd_i8x8([2 2 2 2 2 2 2 2], [-1 -1 -1 -1 -1 -1 -1 -1]) == [1 1 1 1 1 1 1 1]
+
+
+function %iadd_i16x4(i16x4, i16x4) -> i16x4 {
+block0(v0:i16x4, v1:i16x4):
+    v2 = iadd v0, v1
+    return v2
+}
+; run: %iadd_i16x4([1 1 1 1], [1 2 3 4]) == [2 3 4 5]
+; run: %iadd_i16x4([2 2 2 2], [-1 -1 -1 -1]) == [1 1 1 1]
+
+
+function %iadd_i32x2(i32x2, i32x2) -> i32x2 {
+block0(v0:i32x2, v1:i32x2):
+    v2 = iadd v0, v1
+    return v2
+}
+; run: %iadd_i32x2([1 1], [1 2]) == [2 3]
+; run: %iadd_i32x2([2 2], [-1 -1]) == [1 1]