riscv64: Support non 128bit vector sizes (#6266)

* riscv64: Add `Zvl` extensions

* riscv64: Allow lowering SIMD operations that fit in a vector register

* riscv64: Support non 128bit vector sizes

* riscv64: Add Zvl Presets

* riscv64: Precompute `min_vec_reg_size`

cranelift/codegen/meta/src/cdsl/mod.rs

@@ -28,7 +28,7 @@ macro_rules! preset {
     () => {
         vec![]
     };
-    ($($x:ident)&&*) => {
+    ($($x:tt)&&*) => {
         {
             let mut v = Vec::new();
             $(

cranelift/codegen/meta/src/gen_types.rs

@@ -60,7 +60,7 @@ fn emit_types(fmt: &mut srcgen::Formatter) {
 
     // Emit vector definitions for common SIMD sizes.
     // Emit dynamic vector definitions.
-    for vec_size in &[64_u64, 128, 256, 512] {
+    for vec_size in &[16_u64, 32, 64, 128, 256, 512] {
         emit_vectors(*vec_size, fmt);
         emit_dynamic_vectors(*vec_size, fmt);
     }

cranelift/codegen/meta/src/isa/riscv64.rs

@@ -3,6 +3,30 @@ use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
 
 use crate::shared::Definitions as SharedDefinitions;
 
+macro_rules! define_zvl_ext {
+    (DEF: $settings:expr, $size:expr) => {{
+        let name = concat!("has_zvl", $size, "b");
+        let desc = concat!("has extension Zvl", $size, "b?");
+        let comment = concat!(
+            "Zvl",
+            $size,
+            "b: Vector register has a minimum of ",
+            $size,
+            " bits"
+        );
+        $settings.add_bool(&name, &desc, &comment, false)
+    }};
+    ($settings:expr, $size:expr $(, $implies:expr)*) => {{
+        let has_feature = define_zvl_ext!(DEF: $settings, $size);
+
+        let name = concat!("zvl", $size, "b");
+        let desc = concat!("Has a vector register size of at least ", $size, " bits");
+
+        let preset = $settings.add_preset(&name, &desc, preset!(has_feature $( && $implies )*));
+        (has_feature, preset)
+    }};
+}
+
 fn define_settings(_shared: &SettingGroup) -> SettingGroup {
     let mut setting = SettingGroupBuilder::new("riscv64");
 
@@ -56,6 +80,25 @@ fn define_settings(_shared: &SettingGroup) -> SettingGroup {
         false,
     );
 
+    // Zvl*: Minimum Vector Length Standard Extensions
+    // These extension specifiy the minimum number of bits in a vector register.
+    // Since it is a minimum, Zvl64b implies Zvl32b, Zvl128b implies Zvl64b, etc.
+    // The V extension supports a maximum of 64K bits in a single register.
+    //
+    // See: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#181-zvl-minimum-vector-length-standard-extensions
+    let (_, zvl32b) = define_zvl_ext!(setting, 32);
+    let (_, zvl64b) = define_zvl_ext!(setting, 64, zvl32b);
+    let (_, zvl128b) = define_zvl_ext!(setting, 128, zvl64b);
+    let (_, zvl256b) = define_zvl_ext!(setting, 256, zvl128b);
+    let (_, zvl512b) = define_zvl_ext!(setting, 512, zvl256b);
+    let (_, zvl1024b) = define_zvl_ext!(setting, 1024, zvl512b);
+    let (_, zvl2048b) = define_zvl_ext!(setting, 2048, zvl1024b);
+    let (_, zvl4096b) = define_zvl_ext!(setting, 4096, zvl2048b);
+    let (_, zvl8192b) = define_zvl_ext!(setting, 8192, zvl4096b);
+    let (_, zvl16384b) = define_zvl_ext!(setting, 16384, zvl8192b);
+    let (_, zvl32768b) = define_zvl_ext!(setting, 32768, zvl16384b);
+    let (_, _zvl65536b) = define_zvl_ext!(setting, 65536, zvl32768b);
+
     setting.build()
 }