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cranelift: Move most debug-level logs to the trace level

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Cranelift crates have historically been much more verbose with debug-level
logging than most other crates in the Rust ecosystem. We log things like how
many parameters a basic block has, the color of virtual registers during
regalloc, etc. Even for Cranelift hackers, these things are largely only useful
when hacking specifically on Cranelift and looking at a particular test case,
not even when using some Cranelift embedding (such as Wasmtime).

Most of the time, when people want logging for their Rust programs, they do
something like:

    RUST_LOG=debug cargo run

This means that they get all that mostly not useful debug logging out of
Cranelift. So they might want to disable logging for Cranelift, or change it to
a higher log level:

    RUST_LOG=debug,cranelift=info cargo run

The problem is that this is already more annoying to type that `RUST_LOG=debug`,
and that Cranelift isn't one single crate, so you actually have to play
whack-a-mole with naming all the Cranelift crates off the top of your head,
something more like this:

    RUST_LOG=debug,cranelift=info,cranelift_codegen=info,cranelift_wasm=info,...

Therefore, we're changing most of the `debug!` logs into `trace!` logs: anything
that is very Cranelift-internal, unlikely to be useful/meaningful to the
"average" Cranelift embedder, or prints a message for each instruction visited
during a pass. On the other hand, things that just report a one line statistic
for a whole pass, for example, are left as `debug!`. The more verbose the log
messages are, the higher the bar they must clear to be `debug!` rather than
`trace!`.
This commit is contained in:
Nick Fitzgerald
2021-07-26 11:50:16 -07:00
parent ebbe399725
commit 4283d2116d
26 changed files with 156 additions and 166 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
cranelift/codegen/src/binemit/relaxation.rs
View File

@@ -38,7 +38,6 @@ use crate::regalloc::RegDiversions;
use crate::timing;
use crate::CodegenResult;
use core::convert::TryFrom;
use log::debug;
/// Relax branches and compute the final layout of block headers in `func`.
///
@@ -334,7 +333,7 @@ fn relax_branch(
isa: &dyn TargetIsa,
) -> CodeOffset {
let inst = cur.current_inst().unwrap();
debug!(
log::trace!(
"Relaxing [{}] {} for {:#x}-{:#x} range",
encinfo.display(cur.func.encodings[inst]),
cur.func.dfg.display_inst(inst, isa),
@@ -350,7 +349,7 @@ fn relax_branch(
.filter(|&enc| {
let range = encinfo.branch_range(enc).expect("Branch with no range");
if !range.contains(offset, dest_offset) {
debug!(" trying [{}]: out of range", encinfo.display(enc));
log::trace!(" trying [{}]: out of range", encinfo.display(enc));
false
} else if encinfo.operand_constraints(enc)
!= encinfo.operand_constraints(cur.func.encodings[inst])
@@ -360,10 +359,10 @@ fn relax_branch(
// which the existing operands don't satisfy. We can't check for
// validity directly because we don't have a RegDiversions active so
// we don't know which registers are actually in use.
debug!(" trying [{}]: constraints differ", encinfo.display(enc));
log::trace!(" trying [{}]: constraints differ", encinfo.display(enc));
false
} else {
debug!(" trying [{}]: OK", encinfo.display(enc));
log::trace!(" trying [{}]: OK", encinfo.display(enc));
true
}
})

3
cranelift/codegen/src/binemit/shrink.rs
View File

@@ -10,7 +10,6 @@ use crate::ir::Function;
use crate::isa::TargetIsa;
use crate::regalloc::RegDiversions;
use crate::timing;
use log::debug;
/// Pick the smallest valid encodings for instructions.
pub fn shrink_instructions(func: &mut Function, isa: &dyn TargetIsa) {
@@ -58,7 +57,7 @@ pub fn shrink_instructions(func: &mut Function, isa: &dyn TargetIsa) {
if best_enc != enc {
func.encodings[inst] = best_enc;
debug!(
log::trace!(
"Shrunk [{}] to [{}] in {}, reducing the size from {} to {}",
encinfo.display(enc),
encinfo.display(best_enc),

7
cranelift/codegen/src/context.rs
View File

@@ -39,7 +39,6 @@ use crate::verifier::{verify_context, verify_locations, VerifierErrors, Verifier
#[cfg(feature = "souper-harvest")]
use alloc::string::String;
use alloc::vec::Vec;
use log::debug;
#[cfg(feature = "souper-harvest")]
use crate::souper_harvest::do_souper_harvest;
@@ -162,7 +161,7 @@ impl Context {
self.verify_if(isa)?;
let opt_level = isa.flags().opt_level();
debug!(
log::debug!(
"Compiling (opt level {:?}):\n{}",
opt_level,
self.func.display(isa)
@@ -209,7 +208,7 @@ impl Context {
}
let result = self.relax_branches(isa);
debug!("Compiled:\n{}", self.func.display(isa));
log::trace!("Compiled:\n{}", self.func.display(isa));
result
}
}
@@ -377,7 +376,7 @@ impl Context {
self.verify_if(isa)
} else {
legalize_function(&mut self.func, &mut self.cfg, isa);
debug!("Legalized:\n{}", self.func.display(isa));
log::trace!("Legalized:\n{}", self.func.display(isa));
self.verify_if(isa)
}
}

3
cranelift/codegen/src/ir/layout.rs
View File

@@ -11,7 +11,6 @@ use crate::packed_option::PackedOption;
use crate::timing;
use core::cmp;
use core::iter::{IntoIterator, Iterator};
use log::debug;
/// The `Layout` struct determines the layout of blocks and instructions in a function. It does not
/// contain definitions of instructions or blocks, but depends on `Inst` and `Block` entity references
@@ -328,7 +327,7 @@ impl Layout {
next_inst = self.insts[inst].next.expand();
}
}
debug!("Renumbered {} program points", seq / MAJOR_STRIDE);
log::trace!("Renumbered {} program points", seq / MAJOR_STRIDE);
}
}

5
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -10,7 +10,6 @@ use crate::machinst::ty_bits;
use regalloc::{Reg, RegClass, Writable};
use core::convert::TryFrom;
use log::debug;
/// Memory label/reference finalization: convert a MemLabel to a PC-relative
/// offset, possibly emitting relocation(s) as necessary.
@@ -42,7 +41,7 @@ pub fn mem_finalize(
};
let adj = match mem {
&AMode::NominalSPOffset(..) => {
debug!(
log::trace!(
"mem_finalize: nominal SP offset {} + adj {} -> {}",
off,
state.virtual_sp_offset,
@@ -2642,7 +2641,7 @@ impl MachInstEmit for Inst {
}
}
&Inst::VirtualSPOffsetAdj { offset } => {
debug!(
log::trace!(
"virtual sp offset adjusted by {} -> {}",
offset,
state.virtual_sp_offset + offset,

21
cranelift/codegen/src/isa/aarch64/lower.rs
View File

@@ -21,7 +21,6 @@ use crate::isa::aarch64::AArch64Backend;
use super::lower_inst;
use crate::data_value::DataValue;
use log::{debug, trace};
use regalloc::{Reg, Writable};
use smallvec::SmallVec;
use std::cmp;
@@ -275,7 +274,7 @@ fn lower_input_to_regs<C: LowerCtx<I = Inst>>(
ctx: &mut C,
input: InsnInput,
) -> (ValueRegs<Reg>, Type, bool) {
debug!("lower_input_to_regs: input {:?}", input);
log::trace!("lower_input_to_regs: input {:?}", input);
let ty = ctx.input_ty(input.insn, input.input);
let inputs = ctx.get_input_as_source_or_const(input.insn, input.input);
let is_const = inputs.constant.is_some();
@@ -730,7 +729,7 @@ pub(crate) fn lower_pair_address<C: LowerCtx<I = Inst>>(
let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
let offset = args_offset + (offset as i64);
trace!(
log::trace!(
"lower_pair_address: addends64 {:?}, addends32 {:?}, offset {}",
addends64,
addends32,
@@ -791,7 +790,7 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
let mut offset = args_offset + (offset as i64);
trace!(
log::trace!(
"lower_address: addends64 {:?}, addends32 {:?}, offset {}",
addends64,
addends32,
@@ -1194,13 +1193,15 @@ pub(crate) fn maybe_input_insn<C: LowerCtx<I = Inst>>(
op: Opcode,
) -> Option<IRInst> {
let inputs = c.get_input_as_source_or_const(input.insn, input.input);
debug!(
log::trace!(
"maybe_input_insn: input {:?} has options {:?}; looking for op {:?}",
input, inputs, op
input,
inputs,
op
);
if let Some((src_inst, _)) = inputs.inst {
let data = c.data(src_inst);
debug!(" -> input inst {:?}", data);
log::trace!(" -> input inst {:?}", data);
if data.opcode() == op {
return Some(src_inst);
}
@@ -1300,9 +1301,11 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
condcode: IntCC,
output: IcmpOutput,
) -> CodegenResult<IcmpResult> {
debug!(
log::trace!(
"lower_icmp: insn {}, condcode: {}, output: {:?}",
insn, condcode, output
insn,
condcode,
output
);
let rd = output.reg().unwrap_or(writable_zero_reg());

5
cranelift/codegen/src/isa/arm32/inst/emit.rs
View File

@@ -5,7 +5,6 @@ use crate::ir::SourceLoc;
use crate::isa::arm32::inst::*;
use core::convert::TryFrom;
use log::debug;
/// Memory addressing mode finalization: convert "special" modes (e.g.,
/// nominal stack offset) into real addressing modes, possibly by
@@ -25,7 +24,7 @@ pub fn mem_finalize(mem: &AMode, state: &EmitState) -> (SmallVec<[Inst; 4]>, AMo
};
let adj = match mem {
&AMode::NominalSPOffset(..) => {
debug!(
log::trace!(
"mem_finalize: nominal SP offset {} + adj {} -> {}",
off,
state.virtual_sp_offset,
@@ -809,7 +808,7 @@ impl MachInstEmit for Inst {
trap.emit(sink, emit_info, state);
}
&Inst::VirtualSPOffsetAdj { offset } => {
debug!(
log::trace!(
"virtual sp offset adjusted by {} -> {}",
offset,
state.virtual_sp_offset + offset,

3
cranelift/codegen/src/isa/s390x/inst/emit.rs
View File

@@ -7,7 +7,6 @@ use crate::ir::{SourceLoc, TrapCode};
use crate::isa::s390x::inst::*;
use crate::isa::s390x::settings as s390x_settings;
use core::convert::TryFrom;
use log::debug;
use regalloc::{Reg, RegClass};
/// Memory addressing mode finalization: convert "special" modes (e.g.,
@@ -2056,7 +2055,7 @@ impl MachInstEmit for Inst {
}
&Inst::VirtualSPOffsetAdj { offset } => {
debug!(
log::trace!(
"virtual sp offset adjusted by {} -> {}",
offset,
state.virtual_sp_offset + offset

3
cranelift/codegen/src/isa/x64/inst/emit.rs
View File

@@ -12,7 +12,6 @@ use crate::isa::x64::inst::args::*;
use crate::isa::x64::inst::*;
use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel};
use core::convert::TryInto;
use log::debug;
use regalloc::{Reg, Writable};
/// A small helper to generate a signed conversion instruction.
@@ -2548,7 +2547,7 @@ pub(crate) fn emit(
}
Inst::VirtualSPOffsetAdj { offset } => {
debug!(
log::trace!(
"virtual sp offset adjusted by {} -> {}",
offset,
state.virtual_sp_offset + offset

7
cranelift/codegen/src/legalizer/boundary.rs
View File

@@ -32,7 +32,6 @@ use alloc::borrow::Cow;
use alloc::vec::Vec;
use core::mem;
use cranelift_entity::EntityList;
use log::debug;
/// Legalize all the function signatures in `func`.
///
@@ -479,7 +478,7 @@ where
// Reconstruct how `ty` was legalized into the `arg_type` argument.
let conversion = legalize_abi_value(ty, &arg_type);
debug!("convert_from_abi({}): {:?}", ty, conversion);
log::trace!("convert_from_abi({}): {:?}", ty, conversion);
// The conversion describes value to ABI argument. We implement the reverse conversion here.
match conversion {
@@ -488,7 +487,7 @@ where
let abi_ty = ty.half_width().expect("Invalid type for conversion");
let lo = convert_from_abi(pos, abi_ty, None, get_arg);
let hi = convert_from_abi(pos, abi_ty, None, get_arg);
debug!(
log::trace!(
"intsplit {}: {}, {}: {}",
lo,
pos.func.dfg.value_type(lo),
@@ -877,7 +876,7 @@ pub fn handle_return_abi(inst: Inst, func: &mut Function, cfg: &ControlFlowGraph
// the legalized signature. These values should simply be propagated from the entry block
// arguments.
if special_args > 0 {
debug!(
log::trace!(
"Adding {} special-purpose arguments to {}",
special_args,
pos.func.dfg.display_inst(inst, None)

17
cranelift/codegen/src/machinst/abi_impl.rs
View File

@@ -132,7 +132,6 @@ use crate::settings;
use crate::CodegenResult;
use crate::{ir, isa};
use alloc::vec::Vec;
use log::{debug, trace};
use regalloc::{RealReg, Reg, RegClass, Set, SpillSlot, Writable};
use smallvec::{smallvec, SmallVec};
use std::convert::TryFrom;
@@ -547,7 +546,7 @@ impl ABISig {
need_stack_return_area,
)?;
trace!(
log::trace!(
"ABISig: sig {:?} => args = {:?} rets = {:?} arg stack = {} ret stack = {} stack_ret_arg = {:?}",
sig,
args,
@@ -638,7 +637,7 @@ fn get_special_purpose_param_register(
impl<M: ABIMachineSpec> ABICalleeImpl<M> {
/// Create a new body ABI instance.
pub fn new(f: &ir::Function, flags: settings::Flags) -> CodegenResult<Self> {
debug!("ABI: func signature {:?}", f.signature);
log::trace!("ABI: func signature {:?}", f.signature);
let ir_sig = ensure_struct_return_ptr_is_returned(&f.signature);
let sig = ABISig::from_func_sig::<M>(&ir_sig, &flags)?;
@@ -1129,14 +1128,14 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
if let Some(i) = self.sig.stack_ret_arg {
let insts = self.gen_copy_arg_to_regs(i, ValueRegs::one(self.ret_area_ptr.unwrap()));
let inst = insts.into_iter().next().unwrap();
trace!(
log::trace!(
"gen_retval_area_setup: inst {:?}; ptr reg is {:?}",
inst,
self.ret_area_ptr.unwrap().to_reg()
);
Some(inst)
} else {
trace!("gen_retval_area_setup: not needed");
log::trace!("gen_retval_area_setup: not needed");
None
}
}
@@ -1177,7 +1176,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
let islot = slot.get() as i64;
let spill_off = islot * M::word_bytes() as i64;
let sp_off = self.stackslots_size as i64 + spill_off;
trace!("load_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
log::trace!("load_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
// Integer types smaller than word size have been spilled as words below,
// and therefore must be reloaded in the same type.
@@ -1201,7 +1200,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
let islot = slot.get() as i64;
let spill_off = islot * M::word_bytes() as i64;
let sp_off = self.stackslots_size as i64 + spill_off;
trace!("store_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
log::trace!("store_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
// When reloading from a spill slot, we might have lost information about real integer
// types. For instance, on the x64 backend, a zero-extension can become spurious and
@@ -1226,7 +1225,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
let virtual_sp_offset = M::get_virtual_sp_offset_from_state(state);
let nominal_sp_to_fp = M::get_nominal_sp_to_fp(state);
assert!(virtual_sp_offset >= 0);
trace!(
log::trace!(
"spillslots_to_stackmap: slots = {:?}, state = {:?}",
slots,
state
@@ -1334,7 +1333,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
insts.push(M::gen_ret());
}
debug!("Epilogue: {:?}", insts);
log::trace!("Epilogue: {:?}", insts);
insts
}

5
cranelift/codegen/src/machinst/blockorder.rs
View File

@@ -75,7 +75,6 @@ use crate::ir::{Block, Function, Inst, Opcode};
use crate::machinst::lower::visit_block_succs;
use crate::machinst::*;
use log::debug;
use smallvec::SmallVec;
/// Mapping from CLIF BBs to VCode BBs.
@@ -192,7 +191,7 @@ impl LoweredBlock {
impl BlockLoweringOrder {
/// Compute and return a lowered block order for `f`.
pub fn new(f: &Function) -> BlockLoweringOrder {
debug!("BlockLoweringOrder: function body {:?}", f);
log::trace!("BlockLoweringOrder: function body {:?}", f);
// Step 1: compute the in-edge and out-edge count of every block.
let mut block_in_count = SecondaryMap::with_default(0);
@@ -411,7 +410,7 @@ impl BlockLoweringOrder {
lowered_succ_ranges,
orig_map,
};
debug!("BlockLoweringOrder: {:?}", result);
log::trace!("BlockLoweringOrder: {:?}", result);
result
}

7
cranelift/codegen/src/machinst/compile.rs
View File

@@ -6,7 +6,6 @@ use crate::machinst::*;
use crate::settings;
use crate::timing;
use log::debug;
use regalloc::{allocate_registers_with_opts, Algorithm, Options, PrettyPrint};
/// Compile the given function down to VCode with allocated registers, ready
@@ -32,7 +31,7 @@ where
// Creating the vcode string representation may be costly for large functions, so defer its
// rendering.
debug!(
log::trace!(
"vcode from lowering: \n{}",
DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe())))
);
@@ -87,7 +86,7 @@ where
},
)
.map_err(|err| {
debug!(
log::error!(
"Register allocation error for vcode\n{}\nError: {:?}",
vcode.show_rru(Some(b.reg_universe())),
err
@@ -104,7 +103,7 @@ where
vcode.replace_insns_from_regalloc(result);
}
debug!(
log::trace!(
"vcode after regalloc: final version:\n{}",
DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe())))
);

68
cranelift/codegen/src/machinst/lower.rs
View File

@@ -23,7 +23,6 @@ use crate::CodegenResult;
use alloc::boxed::Box;
use alloc::vec::Vec;
use core::convert::TryInto;
use log::debug;
use regalloc::{Reg, StackmapRequestInfo, Writable};
use smallvec::{smallvec, SmallVec};
use std::fmt::Debug;
@@ -358,7 +357,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
if value_regs[param].is_invalid() {
let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
value_regs[param] = regs;
debug!("bb {} param {}: regs {:?}", bb, param, regs);
log::trace!("bb {} param {}: regs {:?}", bb, param, regs);
}
}
for inst in f.layout.block_insts(bb) {
@@ -367,9 +366,12 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
if value_regs[result].is_invalid() {
let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
value_regs[result] = regs;
debug!(
log::trace!(
"bb {} inst {} ({:?}): result regs {:?}",
bb, inst, f.dfg[inst], regs,
bb,
inst,
f.dfg[inst],
regs,
);
}
}
@@ -391,7 +393,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
for ret in &vcode.abi().signature().returns.clone() {
let regs = alloc_vregs(ret.value_type, &mut next_vreg, &mut vcode)?;
retval_regs.push(regs);
debug!("retval gets regs {:?}", regs);
log::trace!("retval gets regs {:?}", regs);
}
// Compute instruction colors, find constant instructions, and find instructions with
@@ -406,16 +408,16 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
for inst in f.layout.block_insts(bb) {
let side_effect = has_lowering_side_effect(f, inst);
debug!("bb {} inst {} has color {}", bb, inst, cur_color);
log::trace!("bb {} inst {} has color {}", bb, inst, cur_color);
if side_effect {
side_effect_inst_entry_colors.insert(inst, InstColor::new(cur_color));
debug!(" -> side-effecting; incrementing color for next inst");
log::trace!(" -> side-effecting; incrementing color for next inst");
cur_color += 1;
}
// Determine if this is a constant; if so, add to the table.
if let Some(c) = is_constant_64bit(f, inst) {
debug!(" -> constant: {}", c);
log::trace!(" -> constant: {}", c);
inst_constants.insert(inst, c);
}
@@ -454,7 +456,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
fn gen_arg_setup(&mut self) {
if let Some(entry_bb) = self.f.layout.entry_block() {
debug!(
log::trace!(
"gen_arg_setup: entry BB {} args are:\n{:?}",
entry_bb,
self.f.dfg.block_params(entry_bb)
@@ -521,7 +523,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
}
fn lower_edge(&mut self, pred: Block, inst: Inst, succ: Block) -> CodegenResult<()> {
debug!("lower_edge: pred {} succ {}", pred, succ);
log::trace!("lower_edge: pred {} succ {}", pred, succ);
let num_args = self.f.dfg.block_params(succ).len();
debug_assert!(num_args == self.f.dfg.inst_variable_args(inst).len());
@@ -558,15 +560,15 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
let dst_regs = self.value_regs[*dst_val];
let input = self.get_value_as_source_or_const(src_val);
debug!("jump arg {} is {}", i, src_val);
log::trace!("jump arg {} is {}", i, src_val);
i += 1;
if let Some(c) = input.constant {
debug!(" -> constant {}", c);
log::trace!(" -> constant {}", c);
const_bundles.push((ty, writable_value_regs(dst_regs), c));
} else {
let src_regs = self.put_value_in_regs(src_val);
debug!(" -> reg {:?}", src_regs);
log::trace!(" -> reg {:?}", src_regs);
// Skip self-assignments. Not only are they pointless, they falsely trigger the
// overlap-check below and hence can cause a lot of unnecessary copying through
// temporaries.
@@ -702,7 +704,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
}
// Are any outputs used at least once?
let value_needed = self.is_any_inst_result_needed(inst);
debug!(
log::trace!(
"lower_clif_block: block {} inst {} ({:?}) is_branch {} side_effect {} value_needed {}",
block,
inst,
@@ -732,7 +734,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
// Normal instruction: codegen if the instruction is side-effecting
// or any of its outputs its used.
if has_side_effect || value_needed {
debug!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
log::trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
backend.lower(self, inst)?;
// Emit value-label markers if needed, to later recover debug
// mappings.
@@ -758,7 +760,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
fn get_value_labels<'a>(&'a self, val: Value, depth: usize) -> Option<&'a [ValueLabelStart]> {
if let Some(ref values_labels) = self.f.dfg.values_labels {
debug!(
log::trace!(
"get_value_labels: val {} -> {} -> {:?}",
val,
self.f.dfg.resolve_aliases(val),
@@ -791,9 +793,11 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
.map(|&ValueLabelStart { label, .. }| label)
.collect::<FxHashSet<_>>();
for label in labels {
debug!(
log::trace!(
"value labeling: defines val {:?} -> reg {:?} -> label {:?}",
val, reg, label,
val,
reg,
label,
);
markers.push(I::gen_value_label_marker(label, reg));
}
@@ -808,7 +812,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
return;
}
debug!(
log::trace!(
"value labeling: srcloc {}: inst {}",
self.srcloc(inst),
inst
@@ -823,7 +827,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
return;
}
debug!("value labeling: block {}", block);
log::trace!("value labeling: block {}", block);
for &arg in self.f.dfg.block_params(block) {
self.emit_value_label_marks_for_value(arg);
}
@@ -870,9 +874,11 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
branches: &SmallVec<[Inst; 2]>,
targets: &SmallVec<[MachLabel; 2]>,
) -> CodegenResult<()> {
debug!(
log::trace!(
"lower_clif_branches: block {} branches {:?} targets {:?}",
block, branches, targets,
block,
branches,
targets,
);
// When considering code-motion opportunities, consider the current
// program point to be the first branch.
@@ -911,7 +917,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
mut self,
backend: &B,
) -> CodegenResult<(VCode<I>, StackmapRequestInfo)> {
debug!("about to lower function: {:?}", self.f);
log::trace!("about to lower function: {:?}", self.f);
// Initialize the ABI object, giving it a temp if requested.
let maybe_tmp = if let Some(temp_ty) = self.vcode.abi().temp_needed() {
@@ -992,15 +998,15 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
// Now that we've emitted all instructions into the VCodeBuilder, let's build the VCode.
let (vcode, stack_map_info) = self.vcode.build();
debug!("built vcode: {:?}", vcode);
log::trace!("built vcode: {:?}", vcode);
Ok((vcode, stack_map_info))
}
fn put_value_in_regs(&mut self, val: Value) -> ValueRegs<Reg> {
debug!("put_value_in_reg: val {}", val);
log::trace!("put_value_in_reg: val {}", val);
let mut regs = self.value_regs[val];
debug!(" -> regs {:?}", regs);
log::trace!(" -> regs {:?}", regs);
assert!(regs.is_valid());
self.value_lowered_uses[val] += 1;
@@ -1025,9 +1031,11 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
/// `get_input()` but starting from the SSA value, which is not exposed to
/// the backend.
fn get_value_as_source_or_const(&self, val: Value) -> NonRegInput {
debug!(
log::trace!(
"get_input_for_val: val {} at cur_inst {:?} cur_scan_entry_color {:?}",
val, self.cur_inst, self.cur_scan_entry_color,
val,
self.cur_inst,
self.cur_scan_entry_color,
);
let inst = match self.f.dfg.value_def(val) {
// OK to merge source instruction if (i) we have a source
@@ -1051,8 +1059,8 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
// prior to the sunk instruction) to sink.
ValueDef::Result(src_inst, result_idx) => {
let src_side_effect = has_lowering_side_effect(self.f, src_inst);
debug!(" -> src inst {}", src_inst);
debug!(" -> has lowering side effect: {}", src_side_effect);
log::trace!(" -> src inst {}", src_inst);
log::trace!(" -> has lowering side effect: {}", src_side_effect);
if !src_side_effect {
// Pure instruction: always possible to sink.
Some((src_inst, result_idx))

27
cranelift/codegen/src/regalloc/coalescing.rs
View File

@@ -22,7 +22,6 @@ use core::cmp;
use core::fmt;
use core::iter;
use core::slice;
use log::debug;
// # Implementation
//
@@ -116,7 +115,7 @@ impl Coalescing {
virtregs: &mut VirtRegs,
) {
let _tt = timing::ra_cssa();
debug!("Coalescing for:\n{}", func.display(isa));
log::trace!("Coalescing for:\n{}", func.display(isa));
self.preorder.compute(domtree, &func.layout);
let mut context = Context {
isa,
@@ -185,7 +184,7 @@ impl<'a> Context<'a> {
continue;
}
debug!(
log::trace!(
" - checking {} params at back-edge {}: {}",
num_params,
pred_block,
@@ -225,7 +224,7 @@ impl<'a> Context<'a> {
if Some(def_block) == self.func.layout.entry_block()
&& self.func.signature.params[def_num].location.is_stack()
{
debug!("-> isolating function stack parameter {}", arg);
log::trace!("-> isolating function stack parameter {}", arg);
let new_arg = self.isolate_arg(pred_block, pred_inst, argnum, arg);
self.virtregs.union(param, new_arg);
continue;
@@ -294,7 +293,7 @@ impl<'a> Context<'a> {
let inst = pos.built_inst();
self.liveness.move_def_locally(param, inst);
debug!(
log::trace!(
"-> inserted {}, following {}({}: {})",
pos.display_inst(inst),
block,
@@ -364,7 +363,7 @@ impl<'a> Context<'a> {
pos.func.dfg.inst_variable_args_mut(pred_inst)[argnum] = copy;
debug!(
log::trace!(
"-> inserted {}, before {}: {}",
pos.display_inst(inst),
pred_block,
@@ -380,7 +379,7 @@ impl<'a> Context<'a> {
/// closure of the relation formed by block parameter-argument pairs found by `union_find_block()`.
fn finish_union_find(&mut self) {
self.virtregs.finish_union_find(None);
debug!("After union-find phase:{}", self.virtregs);
log::trace!("After union-find phase:{}", self.virtregs);
}
}
@@ -411,7 +410,7 @@ impl<'a> Context<'a> {
fn check_vreg(&mut self, vreg: VirtReg) -> bool {
// Order the values according to the dominator pre-order of their definition.
let values = self.virtregs.sort_values(vreg, self.func, self.preorder);
debug!("Checking {} = {}", vreg, DisplayList(values));
log::trace!("Checking {} = {}", vreg, DisplayList(values));
// Now push the values in order to the dominator forest.
// This gives us the closest dominating value def for each of the values.
@@ -432,7 +431,7 @@ impl<'a> Context<'a> {
// `value`, we only have to check if it overlaps the definition.
if self.liveness[parent.value].overlaps_def(node.def, node.block, &self.func.layout) {
// The two values are interfering, so they can't be in the same virtual register.
debug!("-> interference: {} overlaps def of {}", parent, value);
log::trace!("-> interference: {} overlaps def of {}", parent, value);
return false;
}
}
@@ -456,7 +455,7 @@ impl<'a> Context<'a> {
self.cfg,
self.preorder,
);
debug!(
log::trace!(
"Synthesizing {} from {} branches and params {}",
vreg,
self.vcopies.branches.len(),
@@ -544,7 +543,7 @@ impl<'a> Context<'a> {
}
let _vreg = self.virtregs.unify(self.values);
debug!("-> merged into {} = {}", _vreg, DisplayList(self.values));
log::trace!("-> merged into {} = {}", _vreg, DisplayList(self.values));
true
}
@@ -566,7 +565,7 @@ impl<'a> Context<'a> {
// registers and the filtered virtual copies.
let v0 = self.virtregs.congruence_class(&param);
let v1 = self.virtregs.congruence_class(&arg);
debug!(
log::trace!(
" - set 0: {}\n - set 1: {}",
DisplayList(v0),
DisplayList(v1)
@@ -618,7 +617,7 @@ impl<'a> Context<'a> {
if node.set_id != parent.set_id
&& self.liveness[parent.value].reaches_use(inst, node.block, &self.func.layout)
{
debug!(
log::trace!(
" - interference: {} overlaps vcopy at {}:{}",
parent,
node.block,
@@ -643,7 +642,7 @@ impl<'a> Context<'a> {
&& self.liveness[parent.value].overlaps_def(node.def, node.block, &self.func.layout)
{
// The two values are interfering.
debug!(" - interference: {} overlaps def of {}", parent, node.value);
log::trace!(" - interference: {} overlaps def of {}", parent, node.value);
return false;
}
}

41
cranelift/codegen/src/regalloc/coloring.rs
View File

@@ -59,7 +59,6 @@ use crate::regalloc::register_set::RegisterSet;
use crate::regalloc::solver::{Solver, SolverError};
use crate::timing;
use core::mem;
use log::debug;
/// Data structures for the coloring pass.
///
@@ -136,7 +135,7 @@ impl Coloring {
tracker: &mut LiveValueTracker,
) {
let _tt = timing::ra_coloring();
debug!("Coloring for:\n{}", func.display(isa));
log::trace!("Coloring for:\n{}", func.display(isa));
let mut ctx = Context {
usable_regs: isa.allocatable_registers(func),
uses_pinned_reg: isa.flags().enable_pinned_reg(),
@@ -176,7 +175,7 @@ impl<'a> Context<'a> {
/// Visit `block`, assuming that the immediate dominator has already been visited.
fn visit_block(&mut self, block: Block, tracker: &mut LiveValueTracker) {
debug!("Coloring {}:", block);
log::trace!("Coloring {}:", block);
let mut regs = self.visit_block_header(block, tracker);
tracker.drop_dead_params();
@@ -209,7 +208,7 @@ impl<'a> Context<'a> {
if opcode.is_branch() {
// The next instruction is necessarily an unconditional branch.
if let Some(branch) = self.cur.next_inst() {
debug!(
log::trace!(
"Skip coloring {}\n from {}\n with diversions {}",
self.cur.display_inst(branch),
regs.input.display(&self.reginfo),
@@ -230,7 +229,7 @@ impl<'a> Context<'a> {
// Transfer the diversion to the next block.
self.divert
.save_for_block(&mut self.cur.func.entry_diversions, target);
debug!(
log::trace!(
"Set entry-diversion for {} to\n {}",
target,
self.divert.display(&self.reginfo)
@@ -273,7 +272,7 @@ impl<'a> Context<'a> {
// Copy the content of the registered diversions to be reused at the
// entry of this basic block.
self.divert.at_block(&self.cur.func.entry_diversions, block);
debug!(
log::trace!(
"Start {} with entry-diversion set to\n {}",
block,
self.divert.display(&self.reginfo)
@@ -300,7 +299,7 @@ impl<'a> Context<'a> {
let mut regs = AvailableRegs::new(&self.usable_regs);
for lv in live.iter().filter(|lv| !lv.is_dead) {
debug!(
log::trace!(
"Live-in: {}:{} in {}",
lv.value,
lv.affinity.display(&self.reginfo),
@@ -426,7 +425,7 @@ impl<'a> Context<'a> {
tracker: &mut LiveValueTracker,
regs: &mut AvailableRegs,
) -> bool {
debug!(
log::trace!(
"Coloring {}\n from {}",
self.cur.display_inst(inst),
regs.input.display(&self.reginfo),
@@ -490,7 +489,7 @@ impl<'a> Context<'a> {
continue;
}
debug!(
log::trace!(
" kill {} in {} ({} {})",
lv.value,
self.reginfo.display_regunit(reg),
@@ -508,7 +507,7 @@ impl<'a> Context<'a> {
}
// This aligns with the " from" line at the top of the function.
debug!(" glob {}", regs.global.display(&self.reginfo));
log::trace!(" glob {}", regs.global.display(&self.reginfo));
// This flag is set when the solver failed to find a solution for the global defines that
// doesn't interfere with `regs.global`. We need to rewrite all of `inst`s global defines
@@ -564,7 +563,7 @@ impl<'a> Context<'a> {
.solver
.quick_solve(&regs.global, is_reload)
.unwrap_or_else(|_| {
debug!("quick_solve failed for {}", self.solver);
log::trace!("quick_solve failed for {}", self.solver);
self.iterate_solution(
throughs,
&regs.global,
@@ -606,7 +605,7 @@ impl<'a> Context<'a> {
regs.input = output_regs;
for lv in defs {
let loc = self.cur.func.locations[lv.value];
debug!(
log::trace!(
" color {} -> {}{}",
lv.value,
loc.display(&self.reginfo),
@@ -869,7 +868,7 @@ impl<'a> Context<'a> {
let toprc = self.reginfo.toprc(rci);
let reg = self.divert.reg(lv.value, &self.cur.func.locations);
if self.solver.is_fixed_input_conflict(toprc, reg) {
debug!(
log::trace!(
"adding var to divert fixed input conflict for {}",
toprc.info.display_regunit(reg)
);
@@ -895,7 +894,7 @@ impl<'a> Context<'a> {
ConstraintKind::FixedReg(reg) | ConstraintKind::FixedTied(reg) => {
self.add_fixed_output(lv.value, constraint.regclass, reg, throughs);
if !lv.is_local && !global_regs.is_avail(constraint.regclass, reg) {
debug!(
log::trace!(
"Fixed output {} in {}:{} is not available in global regs",
lv.value,
constraint.regclass,
@@ -931,7 +930,7 @@ impl<'a> Context<'a> {
let rc = self.reginfo.rc(rci);
self.add_fixed_output(lv.value, rc, reg, throughs);
if !lv.is_local && !global_regs.is_avail(rc, reg) {
debug!(
log::trace!(
"ABI output {} in {}:{} is not available in global regs",
lv.value,
rc,
@@ -1010,7 +1009,7 @@ impl<'a> Context<'a> {
// We need to make sure that fixed output register is compatible with the
// global register set.
if !lv.is_local && !global_regs.is_avail(constraint.regclass, reg) {
debug!(
log::trace!(
"Tied output {} in {}:{} is not available in global regs",
lv.value,
constraint.regclass,
@@ -1047,7 +1046,7 @@ impl<'a> Context<'a> {
debug_assert!(added, "Ran out of registers in {}", rc);
}
Err(SolverError::Global(_value)) => {
debug!(
log::trace!(
"Not enough global registers for {}, trying as local",
_value
);
@@ -1062,7 +1061,7 @@ impl<'a> Context<'a> {
/// Try to add an `rc` variable to the solver from the `throughs` set.
fn try_add_var(&mut self, rc: RegClass, throughs: &[LiveValue]) -> bool {
debug!("Trying to add a {} reg from {} values", rc, throughs.len());
log::trace!("Trying to add a {} reg from {} values", rc, throughs.len());
for lv in throughs {
if let Affinity::Reg(rci) = lv.affinity {
@@ -1206,7 +1205,7 @@ impl<'a> Context<'a> {
/// the constraints on the instruction operands.
///
fn replace_global_defines(&mut self, inst: Inst, tracker: &mut LiveValueTracker) {
debug!("Replacing global defs on {}", self.cur.display_inst(inst));
log::trace!("Replacing global defs on {}", self.cur.display_inst(inst));
// We'll insert copies *after `inst`. Our caller will move the cursor back.
self.cur.next_inst();
@@ -1253,14 +1252,14 @@ impl<'a> Context<'a> {
lv.endpoint = copy;
lv.is_local = true;
debug!(
log::trace!(
" + {} with {} in {}",
self.cur.display_inst(copy),
local,
loc.display(&self.reginfo)
);
}
debug!("Done: {}", self.cur.display_inst(inst));
log::trace!("Done: {}", self.cur.display_inst(inst));
}
/// Process kills on a ghost instruction.

5
cranelift/codegen/src/regalloc/reload.rs
View File

@@ -22,7 +22,6 @@ use crate::regalloc::liveness::Liveness;
use crate::timing;
use crate::topo_order::TopoOrder;
use alloc::vec::Vec;
use log::debug;
/// Reusable data structures for the reload pass.
pub struct Reload {
@@ -73,7 +72,7 @@ impl Reload {
tracker: &mut LiveValueTracker,
) {
let _tt = timing::ra_reload();
debug!("Reload for:\n{}", func.display(isa));
log::trace!("Reload for:\n{}", func.display(isa));
let mut ctx = Context {
cur: EncCursor::new(func, isa),
encinfo: isa.encoding_info(),
@@ -120,7 +119,7 @@ impl<'a> Context<'a> {
}
fn visit_block(&mut self, block: Block, tracker: &mut LiveValueTracker) {
debug!("Reloading {}:", block);
log::trace!("Reloading {}:", block);
self.visit_block_header(block, tracker);
tracker.drop_dead_params();

31
cranelift/codegen/src/regalloc/solver.rs
View File

@@ -109,7 +109,6 @@ use core::cmp;
use core::fmt;
use core::mem;
use core::u16;
use log::debug;
/// A variable in the constraint problem.
///
@@ -534,7 +533,7 @@ impl Solver {
/// In either case, `to` will not be available for variables on the input side of the
/// instruction.
pub fn reassign_in(&mut self, value: Value, rc: RegClass, from: RegUnit, to: RegUnit) {
debug!(
log::trace!(
"reassign_in({}:{}, {} -> {})",
value,
rc,
@@ -547,7 +546,7 @@ impl Solver {
// added as a variable previously. A fixed constraint beats a variable, so convert it.
if let Some(idx) = self.vars.iter().position(|v| v.value == value) {
let v = self.vars.remove(idx);
debug!("-> converting variable {} to a fixed constraint", v);
log::trace!("-> converting variable {} to a fixed constraint", v);
// The spiller is responsible for ensuring that all constraints on the uses of a
// value are compatible.
debug_assert!(
@@ -580,7 +579,7 @@ impl Solver {
/// This function can only be used before calling `inputs_done()`. Afterwards, more input-side
/// variables can be added by calling `add_killed_var()` and `add_through_var()`
pub fn add_var(&mut self, value: Value, constraint: RegClass, from: RegUnit) {
debug!(
log::trace!(
"add_var({}:{}, from={})",
value,
constraint,
@@ -595,7 +594,7 @@ impl Solver {
///
/// This function should be called after `inputs_done()` only. Use `add_var()` before.
pub fn add_killed_var(&mut self, value: Value, rc: RegClass, from: RegUnit) {
debug!(
log::trace!(
"add_killed_var({}:{}, from={})",
value,
rc,
@@ -610,7 +609,7 @@ impl Solver {
///
/// This function should be called after `inputs_done()` only. Use `add_var()` before.
pub fn add_through_var(&mut self, value: Value, rc: RegClass, from: RegUnit) {
debug!(
log::trace!(
"add_through_var({}:{}, from={})",
value,
rc,
@@ -631,7 +630,7 @@ impl Solver {
if let Some(v) = self.vars.iter_mut().find(|v| v.value == value) {
// We have an existing variable entry for `value`. Combine the constraints.
if let Some(rc) = v.constraint.intersect(rc) {
debug!("-> combining constraint with {} yields {}", v, rc);
log::trace!("-> combining constraint with {} yields {}", v, rc);
v.constraint = rc;
return;
} else {
@@ -643,17 +642,17 @@ impl Solver {
// No variable, then it must be a fixed reassignment.
if let Some(a) = self.assignments.get(value) {
debug!("-> already fixed assignment {}", a);
log::trace!("-> already fixed assignment {}", a);
debug_assert!(rc.contains(a.to), "Incompatible constraints for {}", value);
return;
}
debug!("{}", self);
log::trace!("{}", self);
panic!("Wrong from register for {}", value);
}
let new_var = Variable::new_live(value, rc, from, live_through);
debug!("-> new var: {}", new_var);
log::trace!("-> new var: {}", new_var);
self.regs_in.free(rc, from);
if self.inputs_done && live_through {
@@ -769,7 +768,7 @@ impl Solver {
if is_global {
let mut new_var = Variable::new_live(value, rc, reg, true);
new_var.is_global = true;
debug!("add_tied_input: new tied-global value: {}", new_var);
log::trace!("add_tied_input: new tied-global value: {}", new_var);
self.vars.push(new_var);
self.regs_in.free(rc, reg);
} else {
@@ -900,7 +899,7 @@ impl Solver {
)
});
debug!("real_solve for {}", self);
log::trace!("real_solve for {}", self);
self.find_solution(global_regs, is_reload)
}
@@ -1000,7 +999,7 @@ impl Solver {
.extend(self.assignments.values().filter_map(Move::with_assignment));
if !self.moves.is_empty() {
debug!("collect_moves: {}", DisplayList(&self.moves));
log::trace!("collect_moves: {}", DisplayList(&self.moves));
}
}
@@ -1042,7 +1041,7 @@ impl Solver {
if let Some((rc, reg)) = m.from_reg() {
avail.free(rc, reg);
}
debug!("move #{}: {}", i, m);
log::trace!("move #{}: {}", i, m);
i += 1;
continue;
}
@@ -1076,7 +1075,7 @@ impl Solver {
let m = self.moves[i].clone();
let toprc = m.rc().toprc();
if let Some(reg) = avail.iter(toprc).next() {
debug!(
log::trace!(
"breaking cycle at {} with available {} register {}",
m,
toprc,
@@ -1107,7 +1106,7 @@ impl Solver {
// a last resort.
let slot = num_spill_slots;
num_spill_slots += 1;
debug!("breaking cycle at {} with slot {}", m, slot);
log::trace!("breaking cycle at {} with slot {}", m, slot);
let old_to_reg = self.moves[i].change_to_spill(slot);
self.fills.push(Move::Fill {
value: m.value(),

27
cranelift/codegen/src/regalloc/spilling.rs
View File

@@ -29,7 +29,6 @@ use crate::timing;
use crate::topo_order::TopoOrder;
use alloc::vec::Vec;
use core::fmt;
use log::debug;
/// Return a top-level register class which contains `unit`.
fn toprc_containing_regunit(unit: RegUnit, reginfo: &RegInfo) -> RegClass {
@@ -100,7 +99,7 @@ impl Spilling {
tracker: &mut LiveValueTracker,
) {
let _tt = timing::ra_spilling();
debug!("Spilling for:\n{}", func.display(isa));
log::trace!("Spilling for:\n{}", func.display(isa));
let reginfo = isa.register_info();
let usable_regs = isa.allocatable_registers(func);
let mut ctx = Context {
@@ -128,7 +127,7 @@ impl<'a> Context<'a> {
}
fn visit_block(&mut self, block: Block, tracker: &mut LiveValueTracker) {
debug!("Spilling {}:", block);
log::trace!("Spilling {}:", block);
self.cur.goto_top(block);
self.visit_block_header(block, tracker);
tracker.drop_dead_params();
@@ -205,12 +204,14 @@ impl<'a> Context<'a> {
if let Affinity::Reg(rci) = lv.affinity {
let rc = self.reginfo.rc(rci);
'try_take: while let Err(mask) = self.pressure.take_transient(rc) {
debug!("Need {} reg for block param {}", rc, lv.value);
log::trace!("Need {} reg for block param {}", rc, lv.value);
match self.spill_candidate(mask, liveins) {
Some(cand) => {
debug!(
log::trace!(
"Spilling live-in {} to make room for {} block param {}",
cand, rc, lv.value
cand,
rc,
lv.value
);
self.spill_reg(cand);
}
@@ -218,7 +219,7 @@ impl<'a> Context<'a> {
// We can't spill any of the live-in registers, so we have to spill an
// block argument. Since the current spill metric would consider all the
// block arguments equal, just spill the present register.
debug!("Spilling {} block argument {}", rc, lv.value);
log::trace!("Spilling {} block argument {}", rc, lv.value);
// Since `spill_reg` will free a register, add the current one here.
self.pressure.take(rc);
@@ -236,7 +237,7 @@ impl<'a> Context<'a> {
}
fn visit_inst(&mut self, inst: Inst, block: Block, tracker: &mut LiveValueTracker) {
debug!("Inst {}, {}", self.cur.display_inst(inst), self.pressure);
log::trace!("Inst {}, {}", self.cur.display_inst(inst), self.pressure);
debug_assert_eq!(self.cur.current_inst(), Some(inst));
debug_assert_eq!(self.cur.current_block(), Some(block));
@@ -284,7 +285,7 @@ impl<'a> Context<'a> {
if op.kind != ConstraintKind::Stack {
// Add register def to pressure, spill if needed.
while let Err(mask) = self.pressure.take_transient(op.regclass) {
debug!("Need {} reg from {} throughs", op.regclass, throughs.len());
log::trace!("Need {} reg from {} throughs", op.regclass, throughs.len());
match self.spill_candidate(mask, throughs) {
Some(cand) => self.spill_reg(cand),
None => panic!(
@@ -344,7 +345,7 @@ impl<'a> Context<'a> {
// Only collect the interesting register uses.
if reguse.fixed || reguse.tied || reguse.spilled {
debug!(" reguse: {}", reguse);
log::trace!(" reguse: {}", reguse);
self.reg_uses.push(reguse);
}
}
@@ -378,7 +379,7 @@ impl<'a> Context<'a> {
let mut reguse = RegUse::new(arg, idx, toprc.into());
reguse.fixed = true;
debug!(" reguse: {}", reguse);
log::trace!(" reguse: {}", reguse);
self.reg_uses.push(reguse);
}
}
@@ -452,7 +453,7 @@ impl<'a> Context<'a> {
if need_copy || ru.spilled {
let rc = self.reginfo.rc(ru.rci);
while let Err(mask) = self.pressure.take_transient(rc) {
debug!("Copy of {} reg causes spill", rc);
log::trace!("Copy of {} reg causes spill", rc);
// Spill a live register that is *not* used by the current instruction.
// Spilling a use wouldn't help.
//
@@ -535,7 +536,7 @@ impl<'a> Context<'a> {
let rc = self.reginfo.rc(rci);
self.pressure.free(rc);
self.spills.push(value);
debug!("Spilled {}:{} -> {}", value, rc, self.pressure);
log::trace!("Spilled {}:{} -> {}", value, rc, self.pressure);
} else {
panic!("Cannot spill {} that was already on the stack", value);
}

5
cranelift/codegen/src/timing.rs
View File

@@ -108,7 +108,6 @@ impl fmt::Display for Pass {
#[cfg(feature = "std")]
mod details {
use super::{Pass, DESCRIPTIONS, NUM_PASSES};
use log::debug;
use std::cell::{Cell, RefCell};
use std::fmt;
use std::mem;
@@ -193,7 +192,7 @@ mod details {
/// This function is called by the publicly exposed pass functions.
pub(super) fn start_pass(pass: Pass) -> TimingToken {
let prev = CURRENT_PASS.with(|p| p.replace(pass));
debug!("timing: Starting {}, (during {})", pass, prev);
log::debug!("timing: Starting {}, (during {})", pass, prev);
TimingToken {
start: Instant::now(),
pass,
@@ -205,7 +204,7 @@ mod details {
impl Drop for TimingToken {
fn drop(&mut self) {
let duration = self.start.elapsed();
debug!("timing: Ending {}", self.pass);
log::debug!("timing: Ending {}", self.pass);
let old_cur = CURRENT_PASS.with(|p| p.replace(self.prev));
debug_assert_eq!(self.pass, old_cur, "Timing tokens dropped out of order");
PASS_TIME.with(|rc| {

5
cranelift/codegen/src/unreachable_code.rs
View File

@@ -5,7 +5,6 @@ use crate::dominator_tree::DominatorTree;
use crate::flowgraph::ControlFlowGraph;
use crate::ir;
use crate::timing;
use log::debug;
/// Eliminate unreachable code.
///
@@ -25,14 +24,14 @@ pub fn eliminate_unreachable_code(
continue;
}
debug!("Eliminating unreachable {}", block);
log::trace!("Eliminating unreachable {}", block);
// Move the cursor out of the way and make sure the next lop iteration goes to the right
// block.
pos.prev_block();
// Remove all instructions from `block`.
while let Some(inst) = pos.func.layout.first_inst(block) {
debug!(" - {}", pos.func.dfg.display_inst(inst, None));
log::trace!(" - {}", pos.func.dfg.display_inst(inst, None));
pos.func.layout.remove_inst(inst);
}

3
cranelift/codegen/src/verifier/mod.rs
View File

@@ -79,7 +79,6 @@ use alloc::string::{String, ToString};
use alloc::vec::Vec;
use core::cmp::Ordering;
use core::fmt::{self, Display, Formatter, Write};
use log::debug;
pub use self::cssa::verify_cssa;
pub use self::liveness::verify_liveness;
@@ -2046,7 +2045,7 @@ impl<'a> Verifier<'a> {
verify_flags(self.func, &self.expected_cfg, self.isa, errors)?;
if !errors.is_empty() {
debug!(
log::warn!(
"Found verifier errors in function:\n{}",
pretty_verifier_error(self.func, None, None, errors.clone())
);

1
cranelift/filetests/src/test_stack_maps.rs
View File

@@ -46,7 +46,6 @@ impl SubTest for TestStackMaps {
text.push_str("Stack maps:\n");
text.push('\n');
text.push_str(&sink.text);
log::debug!("FITZGEN:\n{}", text);
run_filecheck(&text, context)
}

5
cranelift/frontend/src/switch.rs
View File

@@ -4,7 +4,6 @@ use alloc::vec::Vec;
use core::convert::TryFrom;
use cranelift_codegen::ir::condcodes::IntCC;
use cranelift_codegen::ir::*;
use log::debug;
type EntryIndex = u128;
@@ -77,7 +76,7 @@ impl Switch {
/// * Between two `ContiguousCaseRange`s there will be at least one entry index.
/// * No `ContiguousCaseRange`s will be empty.
fn collect_contiguous_case_ranges(self) -> Vec<ContiguousCaseRange> {
debug!("build_contiguous_case_ranges before: {:#?}", self.cases);
log::trace!("build_contiguous_case_ranges before: {:#?}", self.cases);
let mut cases = self.cases.into_iter().collect::<Vec<(_, _)>>();
cases.sort_by_key(|&(index, _)| index);
@@ -100,7 +99,7 @@ impl Switch {
last_index = Some(index);
}
debug!(
log::trace!(
"build_contiguous_case_ranges after: {:#?}",
contiguous_case_ranges
);

5
cranelift/src/interpret.rs
View File

@@ -5,7 +5,6 @@ use cranelift_interpreter::environment::FunctionStore;
use cranelift_interpreter::interpreter::{Interpreter, InterpreterState};
use cranelift_interpreter::step::ControlFlow;
use cranelift_reader::{parse_run_command, parse_test, ParseError, ParseOptions};
use log::debug;
use std::path::PathBuf;
use std::{fs, io};
use structopt::StructOpt;
@@ -76,7 +75,7 @@ impl FileInterpreter {
/// Construct a file runner from a CLIF file path.
pub fn from_path(path: impl Into<PathBuf>) -> Result<Self, io::Error> {
let path = path.into();
debug!("New file runner from path: {}:", path.to_string_lossy());
log::trace!("New file runner from path: {}:", path.to_string_lossy());
let contents = fs::read_to_string(&path)?;
Ok(Self {
path: Some(path),
@@ -87,7 +86,7 @@ impl FileInterpreter {
/// Construct a file runner from a CLIF code string. Currently only used for testing.
#[cfg(test)]
pub fn from_inline_code(contents: String) -> Self {
debug!("New file runner from inline code: {}:", &contents[..20]);
log::trace!("New file runner from inline code: {}:", &contents[..20]);
Self {
path: None,
contents,

2
cranelift/wasm/src/func_translator.rs
View File

@@ -79,7 +79,7 @@ impl FuncTranslator {
) -> WasmResult<()> {
let _tt = timing::wasm_translate_function();
let mut reader = body.get_binary_reader();
log::debug!(
log::trace!(
"translate({} bytes, {}{})",
reader.bytes_remaining(),
func.name,