Support wasm select instruction with V128-typed operands on AArch64.
* this requires upgrading to wasmparser 0.67.0. * There are no CLIF side changes because the CLIF `select` instruction is polymorphic enough. * on aarch64, there is unfortunately no conditional-move (csel) instruction on vectors. This patch adds a synthetic instruction `VecCSel` which *does* behave like that. At emit time, this is emitted as an if-then-else diamond (4 insns). * aarch64 implementation is otherwise straightforwards.
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julian-seward1
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9ced345aed
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41e87a2f99
@@ -1016,6 +1016,15 @@ pub enum Inst {
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size: VectorSize,
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},
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/// Vector conditional select, 128 bit. A synthetic instruction, which generates a 4-insn
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/// control-flow diamond.
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VecCSel {
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rd: Writable<Reg>,
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rn: Reg,
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rm: Reg,
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cond: Cond,
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},
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/// Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
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MovToNZCV {
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rn: Reg,
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@@ -1732,6 +1741,11 @@ fn aarch64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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collector.add_def(rd);
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collector.add_use(rn);
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}
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&Inst::VecCSel { rd, rn, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&Inst::FpuCmp32 { rn, rm } | &Inst::FpuCmp64 { rn, rm } => {
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collector.add_use(rn);
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collector.add_use(rm);
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@@ -2343,6 +2357,16 @@ fn aarch64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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map_def(mapper, rd);
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map_use(mapper, rn);
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}
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&mut Inst::VecCSel {
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ref mut rd,
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ref mut rn,
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ref mut rm,
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..
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} => {
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map_def(mapper, rd);
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map_use(mapper, rn);
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map_use(mapper, rm);
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}
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&mut Inst::FpuCmp32 {
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ref mut rn,
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ref mut rm,
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@@ -3591,6 +3615,13 @@ impl Inst {
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format!("ld1r {{ {} }}, [{}]", rd, rn)
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}
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&Inst::VecCSel { rd, rn, rm, cond } => {
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, VectorSize::Size8x16);
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let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size8x16);
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let rm = show_vreg_vector(rm, mb_rru, VectorSize::Size8x16);
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let cond = cond.show_rru(mb_rru);
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format!("vcsel {}, {}, {}, {} (if-then-else diamond)", rd, rn, rm, cond)
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}
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&Inst::MovToNZCV { rn } => {
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let rn = rn.show_rru(mb_rru);
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format!("msr nzcv, {}", rn)
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